Icestorm: STNP (S) measurements

Code:

  stnp s0, s1, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 7 nops): 2.000

Issues: 2.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)
9004	4075	2001	1	1000	1000	1000	1000	8736	4000	2000	1000	1000	2000	2000	1	1000	1000
9004	2507	2001	1	1000	1000	1000	1000	8747	4000	2000	1000	1000	2000	2000	1	1000	1000
9004	2306	2001	1	1000	1000	1000	1000	8749	4000	2000	1000	1000	2000	2000	1	1000	1000
9004	2305	2001	1	1000	1000	1000	1000	8749	4000	2000	1000	1000	2000	2000	1	1000	1000
9004	2305	2001	1	1000	1000	1000	1000	8749	4000	2000	1000	1000	2000	2000	1	1000	1000
9004	2305	2001	1	1000	1000	1000	1000	8749	4000	2000	1000	1000	2000	2000	1	1000	1000
9004	2305	2001	1	1000	1000	1000	1000	8749	4000	2000	1000	1000	2000	2000	1	1000	1000
9004	2305	2001	1	1000	1000	1000	1000	8749	4000	2000	1000	1000	2000	2000	1	1000	1000
9004	2305	2001	1	1000	1000	1000	1000	8749	4000	2000	1000	1000	2000	2000	1	1000	1000
9004	2305	2001	1	1000	1000	1000	1000	8749	4000	2000	1000	1000	2000	2000	1	1000	1000

Count: 8

Code:

  stnp s0, s1, [x6]
  stnp s0, s1, [x6]
  stnp s0, s1, [x6]
  stnp s0, s1, [x6]
  stnp s0, s1, [x6]
  stnp s0, s1, [x6]
  stnp s0, s1, [x6]
  stnp s0, s1, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0376

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160206	80375	160156	101	80037	80018	100	80039	80001	300	1413670	320026	160107	200	80006	80006	200	160012	160012	1	80000	80000	100
160204	83025	160105	101	80004	80000	100	80006	80001	300	1413706	320026	160107	200	80006	80006	200	160012	160012	1	80000	80000	100
160204	83025	160105	101	80004	80000	100	80006	80031	300	1414407	320146	160167	200	80036	80036	200	160012	160012	1	80000	80000	100
160204	83025	160105	101	80004	80000	100	80006	80001	300	1413706	320026	160107	200	80006	80006	200	160012	160012	1	80000	80000	100
160204	83025	160105	101	80004	80000	100	80006	80001	300	1413706	320026	160107	200	80006	80006	200	160012	160012	1	80000	80000	100
160204	83025	160105	101	80004	80000	100	80006	80001	300	1413706	320026	160107	200	80006	80006	200	160012	160012	1	80000	80000	100
160204	83025	160105	101	80004	80000	100	80006	80001	300	1413706	320026	160107	200	80006	80006	200	160012	160012	1	80000	80000	100
160204	83025	160105	101	80004	80000	100	80006	80001	300	1413706	320026	160107	200	80006	80006	200	160012	160012	1	80000	80000	100
160204	83025	160105	101	80004	80000	100	80006	80001	300	1413706	320026	160107	200	80006	80006	200	160012	160012	1	80000	80000	100
138660	87431	138789	3043	67120	68626	3262	67122	80001	300	1413346	320026	160107	200	80006	80006	200	160012	160012	1	80000	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0376

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160026	80332	160065	11	80036	80018	10	80038	80001	30	1413742	320026	160017	20	80006	80006	20	160000	160000	1	80000	80000	10
160024	83029	160011	11	80000	80000	10	80000	80000	30	1413703	320000	160010	20	80000	80000	20	160000	160000	1	80000	80000	10
160024	83025	160011	11	80000	80000	10	80000	80000	30	1413703	320000	160010	20	80000	80000	20	160000	160000	1	80000	80000	10
160024	83025	160011	11	80000	80000	10	80000	80000	30	1413703	320000	160010	20	80000	80000	20	160000	160000	1	80000	80000	10
160025	83086	160063	11	80034	80018	10	80036	80000	30	1413703	320000	160010	20	80000	80000	20	160000	160000	1	80000	80000	10
160024	83025	160011	11	80000	80000	10	80000	80000	30	1413703	320000	160010	20	80000	80000	20	160000	160000	1	80000	80000	10
160024	83025	160011	11	80000	80000	10	80000	80031	30	1414091	320146	160077	20	80036	80036	20	160000	160000	1	80000	80000	10
160024	83025	160011	11	80000	80000	10	80000	80000	30	1413703	320000	160010	20	80000	80000	20	160000	160000	1	80000	80000	10
160024	83025	160011	11	80000	80000	10	80000	80000	30	1413703	320000	160010	20	80000	80000	20	160000	160000	1	80000	80000	10
160024	83025	160011	11	80000	80000	10	80000	73392	248325	1400889	279549	147520	6857	74302	69420	20	160012	160012	1	80000	80000	10

STNP (S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations