Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
stnp q0, q1, [x6, #0x10] nop ; nop ; nop ; nop ; nop ; nop ; nop
mov x0, 0
(no loop instructions)
Retires (minus 7 nops): 2.000
Issues: 2.000
Integer unit issues: 0.001
Load/store unit issues: 2.000
SIMD/FP unit issues: 0.000
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch ldst uop (58) | simd uops in schedulers (5a) | dispatch uop (78) | map ldst uop (7d) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) |
| 9005 | 4129 | 2019 | 1 | 2018 | 2000 | 8781 | 2000 | 2000 | 4000 | 1 | 2000 |
| 9004 | 2389 | 2001 | 1 | 2000 | 2000 | 9211 | 2000 | 2000 | 4000 | 1 | 2000 |
| 9004 | 2302 | 2001 | 1 | 2000 | 2000 | 9197 | 2000 | 2000 | 4000 | 1 | 2000 |
| 9004 | 2302 | 2001 | 1 | 2000 | 2000 | 9197 | 2000 | 2000 | 4000 | 1 | 2000 |
| 9004 | 2309 | 2001 | 1 | 2000 | 2000 | 9197 | 2000 | 2000 | 4000 | 1 | 2000 |
| 9004 | 2302 | 2001 | 1 | 2000 | 2000 | 9197 | 2000 | 2000 | 4000 | 1 | 2000 |
| 9004 | 2302 | 2001 | 1 | 2000 | 2000 | 9197 | 2000 | 2000 | 4000 | 1 | 2000 |
| 9004 | 2302 | 2001 | 1 | 2000 | 2000 | 8950 | 2000 | 2000 | 4000 | 1 | 2000 |
| 9004 | 2310 | 2001 | 1 | 2000 | 2000 | 9182 | 2000 | 2000 | 4000 | 1 | 2000 |
| 9004 | 2303 | 2001 | 1 | 2000 | 2000 | 9243 | 2000 | 2000 | 4000 | 1 | 2000 |
Count: 8
Code:
stnp q0, q1, [x6, #0x10] stnp q0, q1, [x6, #0x10] stnp q0, q1, [x6, #0x10] stnp q0, q1, [x6, #0x10] stnp q0, q1, [x6, #0x10] stnp q0, q1, [x6, #0x10] stnp q0, q1, [x6, #0x10] stnp q0, q1, [x6, #0x10]
mov x7, x6 mov x8, x6 mov x9, x6 mov x10, x6 mov x11, x6 mov x12, x6 mov x13, x6
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 2.0747
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | ? int output thing (e9) | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) |
| 160205 | 160146 | 160119 | 101 | 0 | 160018 | 100 | 0 | 160001 | 300 | 2827668 | 0 | 160101 | 200 | 160008 | 0 | 200 | 320016 | 0 | 1 | 160000 | 0 | 100 |
| 160204 | 166028 | 160101 | 101 | 0 | 160000 | 100 | 0 | 160001 | 300 | 2827704 | 0 | 160101 | 200 | 160008 | 0 | 200 | 320016 | 0 | 1 | 160000 | 0 | 100 |
| 160206 | 166080 | 160135 | 101 | 0 | 160034 | 100 | 0 | 160001 | 300 | 2827740 | 0 | 160101 | 200 | 160008 | 0 | 200 | 320016 | 0 | 1 | 160000 | 0 | 100 |
| 160204 | 166028 | 160101 | 101 | 0 | 160000 | 100 | 0 | 160001 | 300 | 2827704 | 0 | 160101 | 200 | 160008 | 0 | 200 | 320016 | 0 | 1 | 160000 | 0 | 100 |
| 160205 | 166049 | 160118 | 101 | 0 | 160017 | 100 | 0 | 160001 | 300 | 2826804 | 0 | 160101 | 200 | 160008 | 0 | 200 | 320016 | 0 | 1 | 160000 | 0 | 100 |
| 160204 | 165978 | 160101 | 101 | 0 | 160000 | 100 | 0 | 160001 | 300 | 2826804 | 0 | 160101 | 200 | 160008 | 0 | 200 | 320016 | 0 | 1 | 160000 | 0 | 100 |
| 160204 | 165978 | 160101 | 101 | 0 | 160000 | 100 | 0 | 160001 | 300 | 2826804 | 0 | 160101 | 200 | 160008 | 0 | 200 | 320016 | 0 | 1 | 160000 | 0 | 100 |
| 160204 | 165978 | 160101 | 101 | 0 | 160000 | 100 | 0 | 160034 | 300 | 2826968 | 0 | 160134 | 200 | 160048 | 0 | 200 | 320016 | 0 | 1 | 160000 | 0 | 100 |
| 160204 | 165978 | 160101 | 101 | 0 | 160000 | 100 | 0 | 160001 | 300 | 2826804 | 0 | 160101 | 200 | 160008 | 0 | 200 | 320016 | 0 | 1 | 160000 | 0 | 100 |
| 160204 | 165978 | 160101 | 101 | 0 | 160000 | 100 | 0 | 160001 | 300 | 2826804 | 0 | 160101 | 200 | 160008 | 0 | 200 | 320016 | 0 | 1 | 160000 | 0 | 100 |
Result (median cycles for code divided by count): 2.0753
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) |
| 160025 | 160154 | 160029 | 11 | 0 | 160018 | 10 | 0 | 160001 | 30 | 2827562 | 0 | 160011 | 20 | 160008 | 0 | 20 | 320016 | 1 | 160000 | 0 | 10 |
| 160024 | 166021 | 160011 | 11 | 0 | 160000 | 10 | 0 | 160000 | 30 | 2827559 | 0 | 160010 | 20 | 160000 | 0 | 20 | 320000 | 1 | 160000 | 0 | 10 |
| 160024 | 166021 | 160011 | 11 | 0 | 160000 | 10 | 0 | 160034 | 30 | 2827812 | 0 | 160044 | 20 | 160048 | 0 | 20 | 320080 | 1 | 160000 | 0 | 10 |
| 160024 | 166021 | 160011 | 11 | 0 | 160000 | 10 | 0 | 160000 | 30 | 2827499 | 0 | 160010 | 20 | 160000 | 0 | 20 | 320000 | 1 | 160000 | 0 | 10 |
| 160024 | 166021 | 160011 | 11 | 0 | 160000 | 10 | 0 | 160000 | 30 | 2827559 | 0 | 160010 | 20 | 160000 | 0 | 20 | 320000 | 1 | 160000 | 0 | 10 |
| 160024 | 166021 | 160011 | 11 | 0 | 160000 | 10 | 0 | 160000 | 30 | 2827559 | 0 | 160010 | 20 | 160000 | 0 | 20 | 320096 | 1 | 160000 | 0 | 10 |
| 160024 | 166021 | 160011 | 11 | 0 | 160000 | 10 | 0 | 160000 | 30 | 2827559 | 0 | 160010 | 20 | 160000 | 0 | 20 | 320096 | 1 | 160000 | 0 | 10 |
| 160024 | 166021 | 160011 | 11 | 0 | 160000 | 10 | 0 | 160000 | 30 | 2827559 | 0 | 160010 | 20 | 160000 | 0 | 20 | 320000 | 1 | 160000 | 0 | 10 |
| 160024 | 166021 | 160011 | 11 | 0 | 160000 | 10 | 0 | 160000 | 30 | 2827559 | 0 | 160010 | 20 | 160000 | 0 | 20 | 320000 | 1 | 160000 | 0 | 10 |
| 160024 | 166021 | 160011 | 11 | 0 | 160000 | 10 | 0 | 160034 | 30 | 2827546 | 0 | 160044 | 20 | 160048 | 0 | 20 | 320000 | 1 | 160000 | 0 | 10 |