Icestorm: STP (D) measurements

Code:

  stp d0, d1, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 7 nops): 2.000

Issues: 2.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)
9006	4092	2029	1	1014	1014	1014	1000	8739	4000	2000	1000	1000	2000	2000	1	1000	1000
9004	2415	2001	1	1000	1000	1000	1000	8749	4000	2000	1000	1000	2000	2000	1	1000	1000
9004	2308	2001	1	1000	1000	1000	1000	8749	4000	2000	1000	1000	2000	2000	1	1000	1000
9004	2305	2001	1	1000	1000	1000	1000	8749	4000	2000	1000	1000	2000	2000	1	1000	1000
9004	2305	2001	1	1000	1000	1000	1000	8749	4000	2000	1000	1000	2000	2000	1	1000	1000
9004	2305	2001	1	1000	1000	1000	1000	8749	4000	2000	1000	1000	2000	2000	1	1000	1000
9004	2305	2001	1	1000	1000	1000	1000	8749	4000	2000	1000	1000	2000	2000	1	1000	1000
9004	2305	2001	1	1000	1000	1000	1000	8749	4000	2000	1000	1000	2000	2000	1	1000	1000
9004	2305	2001	1	1000	1000	1000	1000	8749	4000	2000	1000	1000	2000	2000	1	1000	1000
9004	2305	2001	1	1000	1000	1000	1000	8749	4000	2000	1000	1000	2000	2000	1	1000	1000

Count: 8

Code:

  stp d0, d1, [x6]
  stp d0, d1, [x6]
  stp d0, d1, [x6]
  stp d0, d1, [x6]
  stp d0, d1, [x6]
  stp d0, d1, [x6]
  stp d0, d1, [x6]
  stp d0, d1, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160206	80148	160155	101	80036	80018	100	80038	80001	300	1359994	320026	160107	200	80006	80006	200	160012	160012	1	80000	80000	100
160204	80045	160105	101	80004	80000	100	80006	80001	300	1360066	320026	160107	200	80006	80006	200	160012	160012	1	80000	80000	100
160204	80045	160105	101	80004	80000	100	80006	80031	300	1360397	320146	160167	200	80036	80036	202	160130	160130	2	80000	80000	100
160204	80045	160105	101	80004	80000	100	80006	80031	300	1361337	320146	160167	200	80036	80036	200	160072	160072	1	80000	80000	100
160205	80232	160201	101	80064	80036	100	80066	80001	300	1360066	320026	160107	200	80006	80006	200	160132	160132	1	80000	80000	100
160204	80045	160105	101	80004	80000	100	80006	80001	300	1360030	320026	160107	200	80006	80006	200	160012	160012	1	80000	80000	100
160204	80045	160105	101	80004	80000	100	80006	80001	300	1360066	320026	160107	200	80006	80006	200	160012	160012	1	80000	80000	100
160204	80174	160153	101	80034	80018	100	80036	80001	300	1360066	320026	160107	200	80006	80006	200	160012	160012	1	80000	80000	100
160204	80045	160105	101	80004	80000	100	80006	80031	300	1361340	320146	160167	200	80036	80036	200	160012	160012	1	80000	80000	100
160204	80173	160153	101	80034	80018	100	80036	80001	300	1360066	320026	160107	200	80006	80006	200	160012	160012	1	80000	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160026	80152	160065	11	80036	80018	10	80038	80001	30	1360066	320026	160017	20	80006	80006	20	160000	160000	1	80000	80000	10
160025	80123	160059	11	80030	80018	10	80030	80000	30	1359955	320000	160010	20	80000	80000	20	160000	160000	1	80000	80000	10
160024	80553	160203	11	80120	80072	10	80120	80000	30	1359955	320000	160010	20	80000	80000	20	160000	160000	1	80000	80000	10
160024	80039	160011	11	80000	80000	10	80000	80000	30	1359973	320000	160010	20	80000	80000	20	160240	160240	1	80000	80000	10
160024	80039	160011	11	80000	80000	10	80000	80000	30	1359955	320000	160010	20	80000	80000	20	160000	160000	1	80000	80000	10
160024	80039	160011	11	80000	80000	10	80000	80000	30	1359955	320000	160010	20	80000	80000	20	160000	160000	1	80000	80000	10
160024	80553	160203	11	80120	80072	10	80120	80000	30	1359955	320000	160010	20	80000	80000	20	160000	160000	1	80000	80000	10
160024	80039	160011	11	80000	80000	10	80000	80000	30	1359955	320000	160010	20	80000	80000	20	160000	160000	1	80000	80000	10
160025	80617	160251	11	80150	80090	10	80150	80000	30	1359955	320000	160010	20	80000	80000	20	160000	160000	1	80000	80000	10
160024	80039	160011	11	80000	80000	10	80000	80000	30	1359955	320000	160010	20	80000	80000	20	160000	160000	1	80000	80000	10

STP (D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations