Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

STP (D)

Test 1: uops

Code:

  stp d0, d1, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 7 nops): 2.000

Issues: 2.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch simd uop (57)dispatch ldst uop (58)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
900640922029110141014101410008739400020001000100020002000110001000
900424152001110001000100010008749400020001000100020002000110001000
900423082001110001000100010008749400020001000100020002000110001000
900423052001110001000100010008749400020001000100020002000110001000
900423052001110001000100010008749400020001000100020002000110001000
900423052001110001000100010008749400020001000100020002000110001000
900423052001110001000100010008749400020001000100020002000110001000
900423052001110001000100010008749400020001000100020002000110001000
900423052001110001000100010008749400020001000100020002000110001000
900423052001110001000100010008749400020001000100020002000110001000

Test 2: throughput

Count: 8

Code:

  stp d0, d1, [x6]
  stp d0, d1, [x6]
  stp d0, d1, [x6]
  stp d0, d1, [x6]
  stp d0, d1, [x6]
  stp d0, d1, [x6]
  stp d0, d1, [x6]
  stp d0, d1, [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
16020680148160155101800368001810080038800013001359994320026160107200800068000620016001216001218000080000100
16020480045160105101800048000010080006800013001360066320026160107200800068000620016001216001218000080000100
16020480045160105101800048000010080006800313001360397320146160167200800368003620216013016013028000080000100
16020480045160105101800048000010080006800313001361337320146160167200800368003620016007216007218000080000100
16020580232160201101800648003610080066800013001360066320026160107200800068000620016013216013218000080000100
16020480045160105101800048000010080006800013001360030320026160107200800068000620016001216001218000080000100
16020480045160105101800048000010080006800013001360066320026160107200800068000620016001216001218000080000100
16020480174160153101800348001810080036800013001360066320026160107200800068000620016001216001218000080000100
16020480045160105101800048000010080006800313001361340320146160167200800368003620016001216001218000080000100
16020480173160153101800348001810080036800013001360066320026160107200800068000620016001216001218000080000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
16002680152160065118003680018108003880001301360066320026160017208000680006201600001600001800008000010
16002580123160059118003080018108003080000301359955320000160010208000080000201600001600001800008000010
16002480553160203118012080072108012080000301359955320000160010208000080000201600001600001800008000010
16002480039160011118000080000108000080000301359973320000160010208000080000201602401602401800008000010
16002480039160011118000080000108000080000301359955320000160010208000080000201600001600001800008000010
16002480039160011118000080000108000080000301359955320000160010208000080000201600001600001800008000010
16002480553160203118012080072108012080000301359955320000160010208000080000201600001600001800008000010
16002480039160011118000080000108000080000301359955320000160010208000080000201600001600001800008000010
16002580617160251118015080090108015080000301359955320000160010208000080000201600001600001800008000010
16002480039160011118000080000108000080000301359955320000160010208000080000201600001600001800008000010