Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

STP (Q)

Test 1: uops

Code:

  stp q0, q1, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 7 nops): 2.000

Issues: 2.000

Integer unit issues: 0.001

Load/store unit issues: 2.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch ldst uop (58)simd uops in schedulers (5a)dispatch uop (78)map ldst uop (7d)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)
900541202019120182000851120002000400012000
900428382001120002000853420002000400012000
900423222001120002000853420002000400012000
900423022001120002000853420002000400012000
900423982017120162000853420002000400012000
900423012001120002000853420002000400012000
900423012001120002000853420002000400012000
900423012001120002000853420002000400012000
900423012001120002000853420002000400012000
900423092001120002000853420002000400012000

Test 2: throughput

Count: 8

Code:

  stp q0, q1, [x6]
  stp q0, q1, [x6]
  stp q0, q1, [x6]
  stp q0, q1, [x6]
  stp q0, q1, [x6]
  stp q0, q1, [x6]
  stp q0, q1, [x6]
  stp q0, q1, [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
1602051601461601191011600181001600013002719938016010120016000802003200161160000100
1602041600451601011011600001001600013002720010016010120016000802003200161160000100
1602041600451601011011600001001600013002720010016010120016000802003200161160000100
1602041600451601011011600001001600343002720120016013420016004802003200161160000100
1602041600451601011011600001001600013002720010016010120016000802003200161160000100
1602041600451601011011600001001600013002720010016010120016000802003200161160000100
1602041600451601011011600001001600013002720010016010120016000802003200161160000100
1602041600451601011011600001001600013002720010016010120016000802003200161160000100
1602041600451601011011600001001600013002720010016010120016000802003200161160000100
1602041600451601011011600001001600013002720010016010120016000802003200161160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
16002516014916002911160018101600343027203901600442016004820320016116000010
16002416004716001111160000101600003027200431600102016000020320000116000010
16002416004716001111160000101600003027200431600102016000020320000116000010
16002416004716001111160000101600003027200431600102016000020320080116000010
16002416004716001111160000101600003027200431600102016000020320096116000010
16002416004716001111160000101600693027202731600792016009020320016116000010
16002416004516001111160000101600003027200071600102016000020320000116000010
16002416004516001111160000101600003027200071600102016000020320000116000010
16002516009616002811160017101600003027199711600102016000020320100116000010
16002416004516001111160000101600003027200071600102016000020320000116000010