Icestorm: STP (post-index, D) measurements

Code:

  stp d0, d1, [x6], #0x10
  nop ; nop ; nop ; nop ; nop ; nop ; nop

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 7 nops): 2.000

Issues: 3.000

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)
9006	4278	3043	1015	1014	1014	1014	1014	1000	3000	8765	4000	3000	1000	1000	2000	2000	1001	1000	1000
9004	2422	3001	1001	1000	1000	1000	1000	1000	3000	8755	4000	3000	1000	1000	2000	2000	1001	1000	1000
9004	2302	3001	1001	1000	1000	1000	1000	1000	3000	8757	4000	3000	1000	1000	2000	2000	1001	1000	1000
9004	2302	3001	1001	1000	1000	1000	1000	1000	3000	8756	4000	3000	1000	1000	2000	2000	1001	1000	1000
9004	2303	3001	1001	1000	1000	1000	1000	1000	3000	8759	4000	3000	1000	1000	2000	2000	1001	1000	1000
9004	2302	3001	1001	1000	1000	1000	1000	1000	3000	8757	4000	3000	1000	1000	2000	2000	1001	1000	1000
9004	2302	3001	1001	1000	1000	1000	1000	1000	3000	8757	4000	3000	1000	1000	2000	2000	1001	1000	1000
9004	2302	3001	1001	1000	1000	1000	1000	1000	3000	8756	4000	3000	1000	1000	2000	2000	1001	1000	1000
9004	2303	3001	1001	1000	1000	1000	1000	1000	3000	8756	4000	3000	1000	1000	2000	2000	1001	1000	1000
9004	2303	3001	1001	1000	1000	1000	1000	1000	3000	8755	4000	3000	1000	1000	2000	2000	1001	1000	1000

Test 2: Latency 3->3

Code:

  stp d0, d1, [x6], #0x10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.1298

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
20224	14292	30900	10412	10308	10180	10413	10310	10003	36892	192309	40030	30117	200	10007	10007	200	20014	20014	10006	10000	10000	100
20204	11311	30111	10106	10005	10000	10107	10007	10000	35690	192948	40026	30112	200	10006	10006	200	20012	20012	10005	10000	10000	100
20204	11315	30109	10105	10004	10000	10106	10006	10000	35692	192858	40026	30112	200	10006	10006	200	20012	20012	10005	10000	10000	100
20204	11328	30109	10105	10004	10000	10106	10006	10000	35695	191544	40026	30112	200	10006	10006	200	20012	20012	10005	10000	10000	100
20204	11240	30109	10105	10004	10000	10106	10006	10000	35692	192876	40026	30112	200	10006	10006	200	20012	20012	10005	10000	10000	100
20204	11291	30109	10105	10004	10000	10106	10006	10000	35692	192318	40026	30112	200	10006	10006	200	20012	20012	10005	10000	10000	100
20204	11444	30109	10105	10004	10000	10106	10006	10002	35690	194302	40026	30114	200	10006	10006	200	20012	20012	10005	10000	10000	100
20204	11318	30109	10105	10004	10000	10106	10006	10000	35689	191454	40026	30112	200	10006	10006	200	20012	20012	10005	10000	10000	100
20204	11245	30109	10105	10004	10000	10106	10006	10000	35689	192120	40026	30112	200	10006	10006	200	20012	20012	10005	10000	10000	100
20204	11277	30109	10105	10004	10000	10106	10006	10000	35696	191598	40026	30112	200	10006	10006	200	20012	20012	10005	10000	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.1330

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
20044	15713	30819	10325	10314	10180	10326	10316	10000	35432	191494	40018	30018	20	10006	10006	20	20000	20000	10001	10000	10000	10
20024	11240	30011	10011	10000	10000	10010	10000	10000	35629	190911	40000	30010	20	10000	10000	20	20000	20000	10001	10000	10000	10
20024	11232	30011	10011	10000	10000	10010	10000	10000	35629	190983	40000	30010	20	10000	10000	20	20000	20000	10001	10000	10000	10
20024	11213	30011	10011	10000	10000	10010	10000	10000	35627	191181	40000	30010	20	10000	10000	20	20000	20000	10001	10000	10000	10
20024	11234	30011	10011	10000	10000	10010	10000	10000	35629	190965	40000	30010	20	10000	10000	20	20000	20000	10001	10000	10000	10
20024	11252	30011	10011	10000	10000	10010	10000	10000	35626	191255	40000	30010	20	10000	10000	20	20000	20000	10001	10000	10000	10
20024	11231	30011	10011	10000	10000	10010	10000	10000	35628	191705	40000	30010	20	10000	10000	20	20000	20000	10001	10000	10000	10
20024	11200	30011	10011	10000	10000	10010	10000	10000	35627	191253	40000	30010	20	10000	10000	20	20000	20000	10001	10000	10000	10
20024	11231	30011	10011	10000	10000	10010	10000	10000	35628	191543	40000	30010	20	10000	10000	20	20000	20000	10001	10000	10000	10
20024	11241	30011	10011	10000	10000	10010	10000	10000	35628	191813	40000	30010	20	10000	10000	20	20000	20000	10001	10000	10000	10

Test 3: throughput

Count: 8

Code:

  stp d0, d1, [x6], #0x10
  stp d0, d1, [x7], #0x10
  stp d0, d1, [x8], #0x10
  stp d0, d1, [x9], #0x10
  stp d0, d1, [x10], #0x10
  stp d0, d1, [x11], #0x10
  stp d0, d1, [x12], #0x10
  stp d0, d1, [x13], #0x10

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160224	82362	240893	80407	80306	80180	80408	80308	80002	240318	1360162	320026	240114	200	80006	80006	200	160012	160012	80005	80000	80000	100
160204	80053	240109	80105	80004	80000	80106	80006	80002	240318	1360113	320026	240114	200	80006	80006	200	160012	160012	80005	80000	80000	100
160204	80053	240109	80105	80004	80000	80106	80006	80002	240318	1360211	320026	240114	200	80006	80006	200	160012	160012	80005	80000	80000	100
160205	80142	240187	80135	80034	80018	80136	80036	80002	240318	1360211	320026	240114	200	80006	80006	200	160012	160012	80005	80000	80000	100
160204	80053	240109	80105	80004	80000	80106	80006	80002	240318	1360211	320026	240114	200	80006	80006	200	160012	160012	80005	80000	80000	100
160204	80053	240109	80105	80004	80000	80106	80006	80002	240318	1360211	320026	240114	200	80006	80006	200	160012	160012	80005	80000	80000	100
160204	80053	240109	80105	80004	80000	80106	80006	80002	240318	1360211	320026	240114	200	80006	80006	200	160012	160012	80005	80000	80000	100
160204	80053	240109	80105	80004	80000	80106	80006	80002	240318	1360211	320026	240114	200	80006	80006	200	160012	160012	80005	80000	80000	100
160205	80142	240187	80135	80034	80018	80136	80036	80002	240318	1360211	320026	240114	200	80006	80006	200	160012	160012	80005	80000	80000	100
160204	80053	240109	80105	80004	80000	80106	80006	80002	240318	1360211	320026	240114	200	80006	80006	200	160012	160012	80005	80000	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160044	82113	240817	80324	80313	80180	80325	80315	80002	240048	1360489	320026	240024	20	80006	80006	20	160000	160000	80001	80000	80000	10
160026	80267	240177	80076	80065	80036	80077	80067	80002	240048	1360367	320026	240024	20	80006	80006	20	160000	160000	80001	80000	80000	10
160024	80056	240011	80011	80000	80000	80010	80000	80000	240030	1360259	320000	240010	20	80000	80000	20	160000	160000	80001	80000	80000	10
160024	80066	240011	80011	80000	80000	80010	80000	80000	240030	1360439	320000	240010	20	80000	80000	20	160000	160000	80001	80000	80000	10
160024	80056	240011	80011	80000	80000	80010	80000	80000	240030	1360259	320000	240010	20	80000	80000	20	160000	160000	80001	80000	80000	10
160024	80056	240011	80011	80000	80000	80010	80000	80000	240030	1360259	320000	240010	20	80000	80000	20	160000	160000	80001	80000	80000	10
160024	80056	240011	80011	80000	80000	80010	80000	80000	240030	1360259	320000	240010	20	80000	80000	20	160072	160072	80035	80000	80000	10
160024	80056	240011	80011	80000	80000	80010	80000	80000	240030	1360259	320000	240010	20	80000	80000	20	160000	160000	80001	80000	80000	10
160024	80056	240011	80011	80000	80000	80010	80000	80000	240030	1360259	320000	240010	20	80000	80000	20	160000	160000	80001	80000	80000	10
160024	80056	240011	80011	80000	80000	80010	80000	80000	240030	1360259	320000	240010	20	80000	80000	20	160000	160000	80001	80000	80000	10

STP (post-index, D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 3->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations