Icestorm: STP (post-index, Q) measurements

Code:

  stp q0, q1, [x6], #0x10
  nop ; nop ; nop ; nop ; nop ; nop ; nop

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 7 nops): 2.000

Issues: 3.000

Integer unit issues: 1.001

Load/store unit issues: 2.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
9005	4280	3031	1013	2018	1014	2000	3000	9693	3000	2000	4000	1001	2000
9004	2396	3001	1001	2000	1000	2000	3000	12849	3000	2000	4000	1001	2000
9004	2306	3001	1001	2000	1000	2000	3000	10845	3000	2000	4000	1001	2000
9004	2306	3001	1001	2000	1000	2000	3000	10845	3000	2000	4000	1001	2000
9004	2306	3001	1001	2000	1000	2000	3000	10845	3000	2000	4000	1001	2000
9004	2306	3001	1001	2000	1000	2000	3000	10961	3000	2000	4000	1001	2000
9004	2310	3001	1001	2000	1000	2000	3000	10961	3000	2000	4000	1001	2000
9004	2306	3001	1001	2000	1000	2000	3000	10477	3000	2000	4000	1001	2000
9004	2306	3001	1001	2000	1000	2000	3000	10845	3000	2000	4000	1001	2000
9004	2310	3001	1001	2000	1000	2000	3000	10845	3000	2000	4000	1001	2000

Test 2: Latency 3->3

Code:

  stp q0, q1, [x6], #0x10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0155

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
20223	22490	30500	10311	20189	10310	20003	35285	341534	30106	200	20010	200	40020	10004	20000	0	100
20204	20115	30103	10103	20000	10102	20001	35275	341308	30103	200	20008	200	40016	10003	20000	0	100
20204	20116	30103	10103	20000	10102	20001	35275	341272	30103	200	20008	200	40016	10003	20000	0	100
20204	20116	30103	10103	20000	10102	20001	35275	341272	30103	200	20008	200	40016	10003	20000	0	100
20204	20116	30103	10103	20000	10102	20001	35275	341272	30103	200	20008	200	40016	10003	20000	0	100
20204	20116	30103	10103	20000	10102	20001	35275	341272	30103	200	20008	200	40016	10003	20000	0	100
20204	20116	30103	10103	20000	10102	20001	35275	341272	30103	200	20008	200	40016	10003	20000	0	100
20204	20118	30103	10103	20000	10102	20001	35275	341290	30103	200	20008	200	40016	10003	20000	0	100
20205	20207	30140	10123	20017	10124	20001	35273	341540	30103	200	20008	200	40016	10003	20000	0	100
20204	20149	30103	10103	20000	10102	20001	35275	341380	30103	200	20008	200	40016	10003	20000	0	100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0130

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
20043	22923	30410	10221	20189	10220	20003	35060	342938	30016	20	20010	20	40000	10001	20000	10
20024	20131	30011	10011	20000	10010	20000	35041	341537	30010	20	20000	20	40000	10001	20000	10
20024	20115	30011	10011	20000	10010	20000	35041	341267	30010	20	20000	20	40000	10001	20000	10
20024	20115	30011	10011	20000	10010	20000	35041	341537	30010	20	20000	20	40000	10001	20000	10
20024	20130	30011	10011	20000	10010	20000	35041	341537	30010	20	20000	20	40000	10001	20000	10
20024	20115	30011	10011	20000	10010	20000	35041	341537	30010	20	20000	20	40000	10001	20000	10
20024	20115	30011	10011	20000	10010	20000	35041	341537	30010	20	20000	20	40000	10001	20000	10
20024	20130	30011	10011	20000	10010	20000	35041	341537	30010	20	20000	20	40000	10001	20000	10
20024	20115	30011	10011	20000	10010	20000	35041	341537	30010	20	20000	20	40000	10001	20000	10
20024	20130	30011	10011	20000	10010	20000	35041	341267	30010	20	20000	20	40000	10001	20000	10

Test 3: throughput

Count: 8

Code:

  stp q0, q1, [x6], #0x10
  stp q0, q1, [x7], #0x10
  stp q0, q1, [x8], #0x10
  stp q0, q1, [x9], #0x10
  stp q0, q1, [x10], #0x10
  stp q0, q1, [x11], #0x10
  stp q0, q1, [x12], #0x10
  stp q0, q1, [x13], #0x10

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160223	162079	240494	80305	160189	80304	160003	240309	2720075	240106	200	160010	200	320096	80019	160000	100
160204	160058	240103	80103	160000	80102	160001	240306	2720066	240103	200	160008	200	320016	80003	160000	100
160204	160049	240103	80103	160000	80102	160001	240306	2720066	240103	200	160008	200	320016	80003	160000	100
160204	160174	240141	80123	160018	80122	160001	240306	2720624	240103	200	160008	200	320016	80003	160000	100
160204	160079	240103	80103	160000	80102	160001	240306	2720606	240103	200	160008	200	320016	80003	160000	100
160204	160079	240103	80103	160000	80102	160001	240306	2720624	240103	200	160008	200	320016	80003	160000	100
160204	160079	240103	80103	160000	80102	160001	240306	2720606	240103	200	160008	200	320176	80043	160000	100
160204	160079	240103	80103	160000	80102	160001	240306	2720606	240103	200	160008	200	320016	80003	160000	100
160204	160081	240103	80103	160000	80102	160001	240306	2720606	240103	200	160008	200	320096	80019	160000	100
160204	160437	240141	80123	160018	80122	160001	240306	2720606	240103	200	160008	200	320016	80003	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0009

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160043	161796	240412	80223	160189	80222	160003	240039	2720112	240016	20	160010	20	320000	80001	160000	10
160024	160045	240011	80011	160000	80010	160000	240030	2719991	240010	20	160000	20	320000	80001	160000	10
160024	160045	240011	80011	160000	80010	160034	240090	2720428	240064	20	160048	20	320000	80001	160000	10
160024	160045	240011	80011	160000	80010	160000	240030	2719991	240010	20	160000	20	320000	80001	160000	10
160024	160045	240011	80011	160000	80010	160000	240030	2719991	240010	20	160000	20	320000	80001	160000	10
160024	160045	240011	80011	160000	80010	160000	240030	2719991	240010	20	160000	20	320000	80001	160000	10
160025	160100	240050	80032	160018	80031	160000	240030	2720045	240010	20	160000	20	320000	80001	160000	10
160024	160045	240011	80011	160000	80010	160000	240030	2719991	240010	20	160000	20	320000	80001	160000	10
160024	160045	240011	80011	160000	80010	160000	240030	2719991	240010	20	160000	20	320000	80001	160000	10
160024	160045	240011	80011	160000	80010	160000	240030	2719991	240010	20	160000	20	320016	80003	160000	10

STP (post-index, Q)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 3->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations