Icestorm: STP (post-index, S) measurements

Code:

  stp s0, s1, [x6], #0x10
  nop ; nop ; nop ; nop ; nop ; nop ; nop

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 7 nops): 2.000

Issues: 3.000

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)
9006	4305	3040	1014	1013	1013	1014	1014	1000	3000	8772	4000	3000	1000	1000	2000	2000	1001	1000	1000
9004	2425	3001	1001	1000	1000	1000	1000	1000	3000	8756	4000	3000	1000	1000	2000	2000	1001	1000	1000
9004	2315	3001	1001	1000	1000	1000	1000	1000	3000	8755	4000	3000	1000	1000	2000	2000	1001	1000	1000
9004	2306	3001	1001	1000	1000	1000	1000	1000	3000	8755	4000	3000	1000	1000	2000	2000	1001	1000	1000
9004	2306	3001	1001	1000	1000	1000	1000	1000	3000	8759	4000	3000	1000	1000	2000	2000	1001	1000	1000
9004	2306	3001	1001	1000	1000	1000	1000	1000	3000	8754	4000	3000	1000	1000	2000	2000	1001	1000	1000
9004	2307	3001	1001	1000	1000	1000	1000	1000	3000	8755	4000	3000	1000	1000	2000	2000	1001	1000	1000
9004	2306	3001	1001	1000	1000	1000	1000	1000	3000	8755	4000	3000	1000	1000	2000	2000	1001	1000	1000
9004	2306	3001	1001	1000	1000	1000	1000	1000	3000	8754	4000	3000	1000	1000	2000	2000	1001	1000	1000
9004	2306	3001	1001	1000	1000	1000	1000	1000	3000	8754	4000	3000	1000	1000	2000	2000	1001	1000	1000

Test 2: Latency 3->3

Code:

  stp s0, s1, [x6], #0x10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.1497

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
20224	14271	30900	10412	10308	10180	10411	10308	10001	37691	193331	40022	30111	200	10007	10007	200	20194	20194	10096	10000	10000	100
20204	11396	30109	10105	10004	10000	10106	10006	10003	36696	192308	40030	30117	200	10007	10007	200	20012	20012	10005	10000	10000	100
20204	11239	30109	10105	10004	10000	10106	10006	10002	35706	191200	40026	30114	200	10006	10006	200	20012	20012	10005	10000	10000	100
20204	11242	30109	10105	10004	10000	10106	10006	10002	35709	190984	40026	30114	200	10006	10006	200	20012	20012	10005	10000	10000	100
20204	11235	30109	10105	10004	10000	10106	10006	10002	35705	192610	40026	30114	200	10006	10006	200	20012	20012	10005	10000	10000	100
20204	11254	30109	10105	10004	10000	10106	10006	10002	35700	190462	40026	30114	200	10006	10006	200	20012	20012	10005	10000	10000	100
20204	11278	30109	10105	10004	10000	10106	10006	10002	35707	191416	40026	30114	200	10006	10006	200	20012	20012	10005	10000	10000	100
20204	11256	30109	10105	10004	10000	10106	10006	10002	35694	192424	40026	30114	200	10006	10006	200	20012	20012	10005	10000	10000	100
20204	11261	30109	10105	10004	10000	10106	10006	10002	35707	190674	40026	30114	200	10006	10006	200	20012	20012	10005	10000	10000	100
20204	11298	30109	10105	10004	10000	10106	10006	10000	35695	197086	40018	30108	200	10006	10006	200	20012	20012	10005	10000	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.1389

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
20044	14416	30815	10323	10312	10180	10322	10312	10002	36635	197505	40030	30026	20	10007	10007	20	20000	20000	10001	10000	10000	10
20024	11406	30011	10011	10000	10000	10010	10000	10000	35429	194694	40000	30010	20	10000	10000	20	20000	20000	10001	10000	10000	10
20024	11392	30011	10011	10000	10000	10010	10000	10000	35430	197546	40000	30010	20	10000	10000	20	20000	20000	10001	10000	10000	10
20024	11396	30011	10011	10000	10000	10010	10000	10000	35437	195062	40000	30010	20	10000	10000	20	20000	20000	10001	10000	10000	10
20024	11510	30011	10011	10000	10000	10010	10000	10000	35434	194496	40000	30010	20	10000	10000	20	20000	20000	10001	10000	10000	10
20024	11344	30011	10011	10000	10000	10010	10000	10000	35434	194190	40000	30010	20	10000	10000	20	20000	20000	10001	10000	10000	10
20024	11412	30011	10011	10000	10000	10010	10000	10000	35430	193704	40000	30010	20	10000	10000	20	20000	20000	10001	10000	10000	10
20024	11387	30011	10011	10000	10000	10010	10000	10000	35434	194298	40000	30010	20	10000	10000	20	20000	20000	10001	10000	10000	10
20024	11346	30011	10011	10000	10000	10010	10000	10000	35432	193416	40000	30010	20	10000	10000	20	20000	20000	10001	10000	10000	10
20024	11356	30011	10011	10000	10000	10010	10000	10000	35430	193704	40000	30010	20	10000	10000	20	20000	20000	10001	10000	10000	10

Test 3: throughput

Count: 8

Code:

  stp s0, s1, [x6], #0x10
  stp s0, s1, [x7], #0x10
  stp s0, s1, [x8], #0x10
  stp s0, s1, [x9], #0x10
  stp s0, s1, [x10], #0x10
  stp s0, s1, [x11], #0x10
  stp s0, s1, [x12], #0x10
  stp s0, s1, [x13], #0x10

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160224	82687	240893	80407	80306	80180	80408	80308	80002	240318	1360162	320026	240114	200	80006	80006	200	160012	160012	80005	80000	80000	100
160204	80065	240109	80105	80004	80000	80106	80006	80002	240318	1360014	320026	240114	200	80006	80006	200	160012	160012	80005	80000	80000	100
160204	80045	240109	80105	80004	80000	80106	80006	80002	240318	1360063	320026	240114	200	80006	80006	200	160012	160012	80005	80000	80000	100
160204	80045	240109	80105	80004	80000	80106	80006	80002	240318	1360063	320026	240114	200	80006	80006	200	160012	160012	80005	80000	80000	100
160204	80045	240109	80105	80004	80000	80106	80006	80002	240318	1360063	320026	240114	200	80006	80006	200	160012	160012	80005	80000	80000	100
160204	80045	240109	80105	80004	80000	80106	80006	80002	240318	1360063	320026	240114	200	80006	80006	200	160012	160012	80005	80000	80000	100
160204	80045	240109	80105	80004	80000	80106	80006	80002	240318	1360063	320026	240114	200	80006	80006	200	160012	160012	80005	80000	80000	100
160204	80045	240109	80105	80004	80000	80106	80006	80002	240318	1360063	320026	240114	200	80006	80006	200	160012	160012	80005	80000	80000	100
160204	80045	240109	80105	80004	80000	80106	80006	80002	240318	1360063	320026	240114	200	80006	80006	200	160012	160012	80005	80000	80000	100
160204	80045	240109	80105	80004	80000	80106	80006	80002	240318	1360063	320026	240114	200	80006	80006	200	160012	160012	80005	80000	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0012

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160044	82336	240819	80325	80314	80180	80326	80316	80002	240048	1360265	320026	240024	20	80006	80006	20	160012	160012	80005	80000	80000	10
160024	80056	240011	80011	80000	80000	80010	80000	80193	249755	1365034	320146	240531	398	80228	80036	20	160000	160000	80001	80000	80000	10
160026	80231	240177	80076	80065	80036	80077	80067	80002	240048	1360497	320026	240024	20	80006	80006	20	160074	160074	80036	80000	80000	10
160025	80150	240099	80046	80035	80018	80047	80037	80000	240030	1360205	320000	240010	20	80000	80000	20	160000	160000	80001	80000	80000	10
160024	80053	240011	80011	80000	80000	80010	80000	80000	240030	1360205	320000	240010	20	80000	80000	20	160000	160000	80001	80000	80000	10
160024	80053	240011	80011	80000	80000	80010	80000	80000	240030	1360205	320000	240010	20	80000	80000	20	160000	160000	80001	80000	80000	10
160024	80053	240011	80011	80000	80000	80010	80000	80000	240030	1360205	320000	240010	20	80000	80000	20	160000	160000	80001	80000	80000	10
160024	80053	240011	80011	80000	80000	80010	80000	80000	240030	1360205	320000	240010	20	80000	80000	20	160000	160000	80001	80000	80000	10
160024	80053	240011	80011	80000	80000	80010	80000	80000	240030	1360205	320000	240010	20	80000	80000	20	160000	160000	80001	80000	80000	10
160024	80053	240011	80011	80000	80000	80010	80000	80032	240138	1361091	320146	240114	20	80036	80036	20	160000	160000	80001	80000	80000	10

STP (post-index, S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 3->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations