Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

STP (post-index, S)

Test 1: uops

Code:

  stp s0, s1, [x6], #0x10
  nop ; nop ; nop ; nop ; nop ; nop ; nop

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 7 nops): 2.000

Issues: 3.000

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
90064305304010141013101310141014100030008772400030001000100020002000100110001000
90042425300110011000100010001000100030008756400030001000100020002000100110001000
90042315300110011000100010001000100030008755400030001000100020002000100110001000
90042306300110011000100010001000100030008755400030001000100020002000100110001000
90042306300110011000100010001000100030008759400030001000100020002000100110001000
90042306300110011000100010001000100030008754400030001000100020002000100110001000
90042307300110011000100010001000100030008755400030001000100020002000100110001000
90042306300110011000100010001000100030008755400030001000100020002000100110001000
90042306300110011000100010001000100030008754400030001000100020002000100110001000
90042306300110011000100010001000100030008754400030001000100020002000100110001000

Test 2: Latency 3->3

Code:

  stp s0, s1, [x6], #0x10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.1497

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
20224142713090010412103081018010411103081000137691193331400223011120010007100072002019420194100961000010000100
20204113963010910105100041000010106100061000336696192308400303011720010007100072002001220012100051000010000100
20204112393010910105100041000010106100061000235706191200400263011420010006100062002001220012100051000010000100
20204112423010910105100041000010106100061000235709190984400263011420010006100062002001220012100051000010000100
20204112353010910105100041000010106100061000235705192610400263011420010006100062002001220012100051000010000100
20204112543010910105100041000010106100061000235700190462400263011420010006100062002001220012100051000010000100
20204112783010910105100041000010106100061000235707191416400263011420010006100062002001220012100051000010000100
20204112563010910105100041000010106100061000235694192424400263011420010006100062002001220012100051000010000100
20204112613010910105100041000010106100061000235707190674400263011420010006100062002001220012100051000010000100
20204112983010910105100041000010106100061000035695197086400183010820010006100062002001220012100051000010000100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.1389

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
20044144163081510323103121018010322103121000236635197505400303002620100071000720200002000010001100001000010
20024114063001110011100001000010010100001000035429194694400003001020100001000020200002000010001100001000010
20024113923001110011100001000010010100001000035430197546400003001020100001000020200002000010001100001000010
20024113963001110011100001000010010100001000035437195062400003001020100001000020200002000010001100001000010
20024115103001110011100001000010010100001000035434194496400003001020100001000020200002000010001100001000010
20024113443001110011100001000010010100001000035434194190400003001020100001000020200002000010001100001000010
20024114123001110011100001000010010100001000035430193704400003001020100001000020200002000010001100001000010
20024113873001110011100001000010010100001000035434194298400003001020100001000020200002000010001100001000010
20024113463001110011100001000010010100001000035432193416400003001020100001000020200002000010001100001000010
20024113563001110011100001000010010100001000035430193704400003001020100001000020200002000010001100001000010

Test 3: throughput

Count: 8

Code:

  stp s0, s1, [x6], #0x10
  stp s0, s1, [x7], #0x10
  stp s0, s1, [x8], #0x10
  stp s0, s1, [x9], #0x10
  stp s0, s1, [x10], #0x10
  stp s0, s1, [x11], #0x10
  stp s0, s1, [x12], #0x10
  stp s0, s1, [x13], #0x10
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
1602248268724089380407803068018080408803088000224031813601623200262401142008000680006200160012160012800058000080000100
1602048006524010980105800048000080106800068000224031813600143200262401142008000680006200160012160012800058000080000100
1602048004524010980105800048000080106800068000224031813600633200262401142008000680006200160012160012800058000080000100
1602048004524010980105800048000080106800068000224031813600633200262401142008000680006200160012160012800058000080000100
1602048004524010980105800048000080106800068000224031813600633200262401142008000680006200160012160012800058000080000100
1602048004524010980105800048000080106800068000224031813600633200262401142008000680006200160012160012800058000080000100
1602048004524010980105800048000080106800068000224031813600633200262401142008000680006200160012160012800058000080000100
1602048004524010980105800048000080106800068000224031813600633200262401142008000680006200160012160012800058000080000100
1602048004524010980105800048000080106800068000224031813600633200262401142008000680006200160012160012800058000080000100
1602048004524010980105800048000080106800068000224031813600633200262401142008000680006200160012160012800058000080000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0012

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
1600448233624081980325803148018080326803168000224004813602653200262400242080006800062016001216001280005800008000010
16002480056240011800118000080000800108000080193249755136503432014624053139880228800362016000016000080001800008000010
1600268023124017780076800658003680077800678000224004813604973200262400242080006800062016007416007480036800008000010
1600258015024009980046800358001880047800378000024003013602053200002400102080000800002016000016000080001800008000010
1600248005324001180011800008000080010800008000024003013602053200002400102080000800002016000016000080001800008000010
1600248005324001180011800008000080010800008000024003013602053200002400102080000800002016000016000080001800008000010
1600248005324001180011800008000080010800008000024003013602053200002400102080000800002016000016000080001800008000010
1600248005324001180011800008000080010800008000024003013602053200002400102080000800002016000016000080001800008000010
1600248005324001180011800008000080010800008000024003013602053200002400102080000800002016000016000080001800008000010
1600248005324001180011800008000080010800008003224013813610913201462401142080036800362016000016000080001800008000010