Icestorm: STP (pre-index, D) measurements

Code:

  stp d0, d1, [x6, #0x10]!
  nop ; nop ; nop ; nop ; nop ; nop ; nop

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 7 nops): 2.000

Issues: 3.000

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)
9006	4349	3043	1015	1014	1014	1014	1014	1000	3000	8768	4000	3000	1000	1000	2000	2000	1001	1000	1000
9004	2400	3001	1001	1000	1000	1000	1000	1000	3000	8757	4000	3000	1000	1000	2000	2000	1001	1000	1000
9004	2306	3001	1001	1000	1000	1000	1000	1000	3000	8759	4000	3000	1000	1000	2000	2000	1001	1000	1000
9004	2316	3001	1001	1000	1000	1000	1000	1000	3000	8760	4000	3000	1000	1000	2000	2000	1001	1000	1000
9004	2306	3001	1001	1000	1000	1000	1000	1000	3000	8759	4000	3000	1000	1000	2000	2000	1001	1000	1000
9004	2585	3001	1001	1000	1000	1000	1000	1000	3000	8763	4000	3000	1000	1000	2000	2000	1001	1000	1000
9004	2313	3001	1001	1000	1000	1000	1000	1000	3000	8762	4000	3000	1000	1000	2000	2000	1001	1000	1000
9004	2306	3001	1001	1000	1000	1000	1000	1000	3000	8761	4000	3000	1000	1000	2000	2000	1001	1000	1000
9004	2306	3001	1001	1000	1000	1000	1000	1000	3000	8761	4000	3000	1000	1000	2000	2000	1001	1000	1000
9004	2369	3001	1001	1000	1000	1000	1000	1000	3000	8762	4000	3000	1000	1000	2000	2000	1001	1000	1000

Test 2: Latency 3->3

Code:

  stp d0, d1, [x6, #0x10]!

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.1419

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
20224	14683	30902	10413	10309	10180	10414	10311	10000	36511	199431	40022	30110	200	10005	10005	200	20014	20014	10006	10000	10000	100
20204	11504	30109	10105	10004	10000	10106	10006	10002	35696	200002	40026	30114	200	10006	10006	200	20012	20012	10005	10000	10000	100
20204	11560	30109	10105	10004	10000	10106	10006	10000	35692	197844	40018	30108	200	10006	10006	200	20012	20012	10005	10000	10000	100
20204	11605	30105	10103	10002	10000	10102	10002	10001	35699	199395	40026	30113	200	10006	10006	200	20012	20012	10005	10000	10000	100
20204	11813	30109	10105	10004	10000	10106	10006	10001	35695	192882	40026	30113	200	10006	10006	200	20012	20012	10005	10000	10000	100
20204	11671	30109	10105	10004	10000	10106	10006	10000	35677	190068	40018	30108	200	10004	10004	200	20012	20012	10005	10000	10000	100
20204	11531	30109	10105	10004	10000	10106	10006	10000	35658	194658	40018	30108	200	10006	10006	200	20012	20012	10005	10000	10000	100
20204	11455	30109	10105	10004	10000	10106	10006	10002	35682	199197	40026	30114	200	10006	10006	200	20012	20012	10005	10000	10000	100
20204	11634	30109	10105	10004	10000	10106	10006	10001	35655	198758	40026	30113	200	10006	10006	200	20012	20012	10005	10000	10000	100
20204	11690	30109	10105	10004	10000	10106	10006	10002	35687	199467	40026	30114	200	10006	10006	200	20012	20012	10005	10000	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.1379

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
20044	15521	30813	10322	10311	10180	10321	10311	10001	36700	194729	40026	30023	20	10006	10006	20	20000	20000	10001	10000	10000	10
20024	11391	30011	10011	10000	10000	10010	10000	10000	35625	194580	40000	30010	20	10000	10000	20	20000	20000	10001	10000	10000	10
20024	11379	30011	10011	10000	10000	10010	10000	10000	35625	194301	40000	30010	20	10000	10000	20	20000	20000	10001	10000	10000	10
20024	11418	30011	10011	10000	10000	10010	10000	10000	35623	193391	40000	30010	20	10000	10000	20	20000	20000	10001	10000	10000	10
20024	11349	30011	10011	10000	10000	10010	10000	10000	35628	193337	40000	30010	20	10000	10000	20	20000	20000	10001	10000	10000	10
20024	11352	30011	10011	10000	10000	10010	10000	10000	35625	194058	40000	30010	20	10000	10000	20	20000	20000	10001	10000	10000	10
20024	11413	30011	10011	10000	10000	10010	10000	10000	35623	193320	40000	30010	20	10000	10000	20	20000	20000	10001	10000	10000	10
20024	11337	30011	10011	10000	10000	10010	10000	10000	35622	194273	40000	30010	20	10000	10000	20	20000	20000	10001	10000	10000	10
20024	11368	30011	10011	10000	10000	10010	10000	10000	35625	194508	40000	30010	20	10000	10000	20	20000	20000	10001	10000	10000	10
20024	11380	30011	10011	10000	10000	10010	10000	10000	35622	194509	40000	30010	20	10000	10000	20	20000	20000	10001	10000	10000	10

Test 3: throughput

Count: 8

Code:

  stp d0, d1, [x6, #0x10]!
  stp d0, d1, [x7, #0x10]!
  stp d0, d1, [x8, #0x10]!
  stp d0, d1, [x9, #0x10]!
  stp d0, d1, [x10, #0x10]!
  stp d0, d1, [x11, #0x10]!
  stp d0, d1, [x12, #0x10]!
  stp d0, d1, [x13, #0x10]!

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160224	82574	240893	80407	80306	80180	80408	80308	80002	240318	1360265	320026	240114	200	80006	80006	200	160012	160012	80005	80000	80000	100
160204	80056	240109	80105	80004	80000	80106	80006	80002	240318	1360117	320026	240114	200	80006	80006	200	160012	160012	80005	80000	80000	100
160204	80048	240109	80105	80004	80000	80106	80006	80002	240318	1360117	320026	240114	200	80006	80006	200	160012	160012	80005	80000	80000	100
160204	80048	240109	80105	80004	80000	80106	80006	80002	240318	1360117	320026	240114	200	80006	80006	200	160072	160072	80035	80000	80000	100
160204	80056	240109	80105	80004	80000	80106	80006	80002	240318	1360117	320026	240114	200	80006	80006	200	160012	160012	80005	80000	80000	100
160204	80048	240109	80105	80004	80000	80106	80006	80002	240318	1360117	320026	240114	200	80006	80006	200	160012	160012	80005	80000	80000	100
160204	80049	240109	80105	80004	80000	80106	80006	80002	240318	1360211	320026	240114	200	80006	80006	200	160012	160012	80005	80000	80000	100
160204	80045	240109	80105	80004	80000	80106	80006	80002	240318	1360063	320026	240114	200	80006	80006	200	160012	160012	80005	80000	80000	100
160204	80045	240109	80105	80004	80000	80106	80006	80002	240318	1360063	320026	240114	200	80006	80006	200	160012	160012	80005	80000	80000	100
160204	80045	240109	80105	80004	80000	80106	80006	80002	240318	1360063	320026	240114	200	80006	80006	200	160012	160012	80005	80000	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0012

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160044	82159	240817	80324	80313	80180	80325	80315	80003	240051	1360298	320030	240027	20	80007	80007	20	160000	160000	80001	80000	80000	10
160024	80053	240011	80011	80000	80000	80010	80000	80000	240030	1360205	320000	240010	20	80000	80000	20	160000	160000	80001	80000	80000	10
160025	80222	240097	80045	80034	80018	80046	80036	80000	240030	1361231	320000	240010	20	80000	80000	20	160000	160000	80001	80000	80000	10
160024	80100	240011	80011	80000	80000	80010	80000	80000	240030	1361231	320000	240010	20	80000	80000	20	160000	160000	80001	80000	80000	10
160024	80098	240011	80011	80000	80000	80010	80000	80000	240030	1360997	320000	240010	20	80000	80000	20	160072	160072	80035	80000	80000	10
160024	80098	240011	80011	80000	80000	80010	80000	80000	240030	1361087	320000	240010	20	80000	80000	20	160000	160000	80001	80000	80000	10
160024	80098	240011	80011	80000	80000	80010	80000	80000	240030	1361015	320000	240010	20	80000	80000	20	160000	160000	80001	80000	80000	10
160024	80098	240011	80011	80000	80000	80010	80000	80000	240030	1361015	320000	240010	20	80000	80000	20	160000	160000	80001	80000	80000	10
160024	80098	240011	80011	80000	80000	80010	80000	80000	240030	1361015	320000	240010	20	80000	80000	20	160000	160000	80001	80000	80000	10
160024	80098	240011	80011	80000	80000	80010	80000	80000	240030	1361015	320000	240010	20	80000	80000	20	160000	160000	80001	80000	80000	10

STP (pre-index, D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 3->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations