Icestorm: STP (pre-index, Q) measurements

Code:

  stp q0, q1, [x6, #0x10]!
  nop ; nop ; nop ; nop ; nop ; nop ; nop

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 7 nops): 2.000

Issues: 3.000

Integer unit issues: 1.001

Load/store unit issues: 2.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
9005	4270	3033	1015	2018	1014	2000	3000	9961	3000	2000	4000	1001	2000
9004	2415	3001	1001	2000	1000	2000	3000	10936	3000	2000	4000	1001	2000
9004	2316	3001	1001	2000	1000	2000	3000	11368	3000	2000	4000	1001	2000
9004	2307	3001	1001	2000	1000	2000	3000	10958	3000	2000	4000	1001	2000
9004	2307	3001	1001	2000	1000	2000	3000	10750	3000	2000	4000	1001	2000
9004	2316	3001	1001	2000	1000	2000	3000	10810	3000	2000	4000	1001	2000
9004	2321	3001	1001	2000	1000	2000	3000	11029	3000	2000	4000	1001	2000
9004	2315	3001	1001	2000	1000	2000	3000	10847	3000	2000	4000	1001	2000
9004	2311	3001	1001	2000	1000	2000	3000	11312	3000	2000	4000	1001	2000
9004	2313	3001	1001	2000	1000	2000	3000	11207	3000	2000	4000	1001	2000

Test 2: Latency 3->3

Code:

  stp q0, q1, [x6, #0x10]!

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0136

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
20223	22625	30499	10310	20189	10309	20003	35283	342343	30106	200	20010	200	40020	10004	20000	0	100
20204	20169	30103	10103	20000	10102	20001	35275	342028	30103	200	20008	200	40016	10003	20000	0	100
20204	20163	30103	10103	20000	10102	20001	35275	341992	30103	200	20008	200	40016	10003	20000	0	100
20204	20158	30103	10103	20000	10102	20001	35275	342028	30103	200	20008	200	40016	10003	20000	0	100
20204	20156	30103	10103	20000	10102	20001	35275	341992	30103	200	20008	200	40016	10003	20000	0	100
20204	20158	30103	10103	20000	10102	20001	35275	342028	30103	200	20008	200	40016	10003	20000	0	100
20204	20156	30103	10103	20000	10102	20001	35275	343450	30103	200	20008	200	40016	10003	20000	0	100
20204	20325	30103	10103	20000	10102	20001	35275	343180	30103	200	20008	9216	35910	11654	18395	4	5460
20204	20476	30102	10102	20000	10103	20001	35275	341596	30103	200	20008	200	40020	10004	20000	0	100
20204	20134	30103	10103	20000	10102	20001	35275	341614	30103	200	20008	200	40016	10003	20000	0	100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0141

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
20043	23006	30407	10218	20189	10217	20003	35058	342073	30016	20	20010	20	40000	10001	20000	10
20024	20125	30011	10011	20000	10010	20000	35041	341429	30010	20	20000	20	40000	10001	20000	10
20024	20124	30011	10011	20000	10010	20000	35041	341429	30010	20	20000	20	40000	10001	20000	10
20024	20124	30011	10011	20000	10010	20000	35041	341429	30010	20	20000	20	40000	10001	20000	10
20024	20124	30011	10011	20000	10010	20000	35041	341429	30010	20	20000	20	40000	10001	20000	10
20024	20124	30011	10011	20000	10010	20000	35041	341429	30010	20	20000	20	40000	10001	20000	10
20024	20124	30011	10011	20000	10010	20000	35041	341429	30010	20	20000	20	40000	10001	20000	10
20024	20124	30011	10011	20000	10010	20000	35041	341429	30010	20	20000	20	40000	10001	20000	10
20024	20124	30011	10011	20000	10010	20000	35041	341429	30010	20	20000	20	40000	10001	20000	10
20024	20124	30011	10011	20000	10010	20000	35041	341429	30010	20	20000	20	40000	10001	20000	10

Test 3: throughput

Count: 8

Code:

  stp q0, q1, [x6, #0x10]!
  stp q0, q1, [x7, #0x10]!
  stp q0, q1, [x8, #0x10]!
  stp q0, q1, [x9, #0x10]!
  stp q0, q1, [x10, #0x10]!
  stp q0, q1, [x11, #0x10]!
  stp q0, q1, [x12, #0x10]!
  stp q0, q1, [x13, #0x10]!

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160224	161969	240527	80321	160206	80322	160001	240306	2720082	0	240103	200	160008	0	200	320016	80003	160000	100
160204	160051	240103	80103	160000	80102	160034	240360	2720516	0	240154	200	160048	0	200	320016	80003	160000	100
160204	160051	240103	80103	160000	80102	160034	240360	2720804	0	240154	200	160048	0	200	320016	80003	160000	100
160205	160127	240136	80119	160017	80120	160001	240306	2720118	0	240103	200	160008	0	200	320016	80003	160000	100
160204	160053	240103	80103	160000	80102	160001	240306	2720154	0	240103	200	160008	0	200	320016	80003	160000	100
160204	160053	240103	80103	160000	80102	160001	240306	2720154	0	240103	200	160008	0	200	320016	80003	160000	100
160204	160053	240103	80103	160000	80102	160001	240306	2720154	0	240103	200	160008	0	200	320016	80003	160000	100
160205	160100	240136	80119	160017	80120	160001	240306	2720154	0	240103	200	160008	0	200	320016	80003	160000	100
160204	160053	240103	80103	160000	80102	160001	240306	2720154	0	240103	200	160008	0	200	320016	80003	160000	100
160204	160053	240103	80103	160000	80102	160001	240306	2720154	0	240103	200	160008	0	200	320016	80003	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160024	160126	240013	80013	160000	80012	160000	240030	2720078	240010	20	160000	20	320000	80001	160000	0	10
160024	160051	240011	80011	160000	80010	160000	240030	2720115	240010	20	160000	20	320000	80001	160000	0	10
160024	160051	240011	80011	160000	80010	160000	240030	2720115	240010	20	160000	20	320000	80001	160000	0	10
160024	160051	240011	80011	160000	80010	160000	240030	2720115	240010	20	160000	20	320000	80001	160000	0	10
160024	160051	240011	80011	160000	80010	160000	240030	2720115	240010	20	160000	20	320000	80001	160000	0	10
160024	160051	240011	80011	160000	80010	160000	240030	2720115	240010	20	160000	20	320000	80001	160000	0	10
160024	160051	240011	80011	160000	80010	160000	240030	2720115	240010	20	160000	20	320000	80001	160000	0	10
160025	160098	240046	80029	160017	80030	160000	240030	2719955	240010	20	160000	20	320000	80001	160000	0	10
160024	160051	240011	80011	160000	80010	160000	240030	2720115	240010	20	160000	20	320000	80001	160000	0	10
160024	160051	240011	80011	160000	80010	160001	240036	2720477	240013	20	160008	20	320016	80003	160000	0	10

STP (pre-index, Q)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 3->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations