Icestorm: STP (pre-index, S) measurements

Code:

  stp s0, s1, [x6, #0x10]!
  nop ; nop ; nop ; nop ; nop ; nop ; nop

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 7 nops): 2.000

Issues: 3.000

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)
9006	4238	3043	1015	1014	1014	1014	1014	1000	3000	8773	4000	3000	1000	1000	2000	2000	1001	1000	1000
9004	2431	3001	1001	1000	1000	1000	1000	1000	3000	8762	4000	3000	1000	1000	2000	2000	1001	1000	1000
9004	2325	3001	1001	1000	1000	1000	1000	1000	3000	8770	4000	3000	1000	1000	2000	2000	1001	1000	1000
9004	2306	3001	1001	1000	1000	1000	1000	1000	3000	8816	4000	3000	1000	1000	2000	2000	1001	1000	1000
9004	2306	3001	1001	1000	1000	1000	1000	1000	3000	8775	4000	3000	1000	1000	2000	2000	1001	1000	1000
9004	2306	3001	1001	1000	1000	1000	1000	1000	3000	8762	4000	3000	1000	1000	2000	2000	1001	1000	1000
9004	2306	3001	1001	1000	1000	1000	1000	1000	3000	8806	4000	3000	1000	1000	2000	2000	1001	1000	1000
9004	2306	3001	1001	1000	1000	1000	1000	1000	3000	8762	4000	3000	1000	1000	2000	2000	1001	1000	1000
9004	2306	3001	1001	1000	1000	1000	1000	1000	3000	8798	4000	3000	1000	1000	2000	2000	1001	1000	1000
9004	2306	3001	1001	1000	1000	1000	1000	1000	3000	8762	4000	3000	1000	1000	2000	2000	1001	1000	1000

Test 2: Latency 3->3

Code:

  stp s0, s1, [x6, #0x10]!

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.1379

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
20224	15038	30900	10412	10308	10180	10411	10308	10002	38276	194183	40030	30116	200	10007	10007	200	20014	20014	10006	10000	10000	100
20204	11372	30109	10105	10004	10000	10106	10006	10001	35749	193796	40026	30113	200	10006	10006	200	20012	20012	10005	10000	10000	100
20204	11371	30109	10105	10004	10000	10106	10006	10001	35746	194410	40026	30113	200	10006	10006	200	20012	20012	10005	10000	10000	100
20204	11367	30109	10105	10004	10000	10106	10006	10001	35745	194428	40026	30113	200	10006	10006	200	20012	20012	10005	10000	10000	100
20204	11412	30109	10105	10004	10000	10106	10006	10001	35748	193600	40026	30113	200	10006	10006	200	20012	20012	10005	10000	10000	100
20204	11376	30109	10105	10004	10000	10106	10006	10001	35746	194032	40026	30113	200	10006	10006	200	20012	20012	10005	10000	10000	100
20204	11399	30109	10105	10004	10000	10106	10006	10001	35746	193798	40026	30113	200	10006	10006	200	20012	20012	10005	10000	10000	100
20204	11379	30109	10105	10004	10000	10106	10006	10001	35747	194824	40026	30113	200	10006	10006	200	20012	20012	10005	10000	10000	100
20204	11391	30109	10105	10004	10000	10106	10006	10001	35745	194086	40026	30113	200	10006	10006	200	20012	20012	10005	10000	10000	100
20204	11390	30109	10105	10004	10000	10106	10006	10001	35748	194662	40026	30113	200	10006	10006	200	20012	20012	10005	10000	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.1384

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
20044	14977	30813	10322	10311	10180	10323	10313	10001	35287	194310	40026	30023	20	10006	10006	20	20000	20000	10001	10000	10000	10
20024	11384	30011	10011	10000	10000	10010	10000	10000	35623	193590	40000	30010	20	10000	10000	20	20000	20000	10001	10000	10000	10
20024	11360	30011	10011	10000	10000	10010	10000	10000	35623	193842	40000	30010	20	10000	10000	20	20000	20000	10001	10000	10000	10
20024	11386	30011	10011	10000	10000	10010	10000	10000	35624	194022	40000	30010	20	10000	10000	20	20000	20000	10001	10000	10000	10
20024	11380	30011	10011	10000	10000	10010	10000	10000	35616	195255	40000	30010	20	10000	10000	20	20000	20000	10001	10000	10000	10
20024	11478	30011	10011	10000	10000	10010	10000	10000	35628	194328	40000	30010	20	10000	10000	20	20000	20000	10001	10000	10000	10
20024	11632	30011	10011	10000	10000	10010	10000	10000	35623	194617	40000	30010	20	10000	10000	20	20000	20000	10001	10000	10000	10
20024	11367	30011	10011	10000	10000	10010	10000	10000	35590	193841	40000	30010	20	10000	10000	20	20000	20000	10001	10000	10000	10
20024	11445	30011	10011	10000	10000	10010	10000	10000	35624	193860	40000	30010	20	10000	10000	20	20000	20000	10001	10000	10000	10
20024	11366	30011	10011	10000	10000	10010	10000	10000	35625	194112	40000	30010	20	10000	10000	20	20000	20000	10001	10000	10000	10

Test 3: throughput

Count: 8

Code:

  stp s0, s1, [x6, #0x10]!
  stp s0, s1, [x7, #0x10]!
  stp s0, s1, [x8, #0x10]!
  stp s0, s1, [x9, #0x10]!
  stp s0, s1, [x10, #0x10]!
  stp s0, s1, [x11, #0x10]!
  stp s0, s1, [x12, #0x10]!
  stp s0, s1, [x13, #0x10]!

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160224	82071	240893	80407	80306	80180	80408	80308	80002	240318	1360265	320026	240114	200	80006	80006	200	160012	160012	80005	80000	80000	100
160204	80056	240109	80105	80004	80000	80106	80006	80002	240318	1360265	320026	240114	200	80006	80006	200	160012	160012	80005	80000	80000	100
160204	80056	240109	80105	80004	80000	80106	80006	80032	240408	1361076	320146	240204	200	80036	80036	200	160012	160012	80005	80000	80000	100
160204	80056	240109	80105	80004	80000	80106	80006	80002	240318	1360265	320026	240114	200	80006	80006	200	160012	160012	80005	80000	80000	100
160204	80056	240109	80105	80004	80000	80106	80006	80002	240318	1360265	320026	240114	200	80006	80006	200	160012	160012	80005	80000	80000	100
160204	80056	240109	80105	80004	80000	80106	80006	80002	240318	1360265	320026	240114	200	80006	80006	200	160072	160072	80035	80000	80000	100
160204	80058	240109	80105	80004	80000	80106	80006	80003	240321	1360519	320030	240117	200	80007	80007	200	160012	160012	80005	80000	80000	100
160204	80056	240109	80105	80004	80000	80106	80006	80002	240318	1360216	320026	240114	200	80006	80006	200	160012	160012	80005	80000	80000	100
160204	80056	240109	80105	80004	80000	80106	80006	80002	240318	1360265	320026	240114	200	80006	80006	200	160012	160012	80005	80000	80000	100
160204	80056	240109	80105	80004	80000	80106	80006	80002	240318	1360543	320026	240114	200	80006	80006	200	160012	160012	80005	80000	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160044	82053	240817	80324	80313	80180	80325	80315	80002	240048	1360211	320026	240024	20	80006	80006	20	160012	160012	80005	80000	80000	10
160024	80045	240011	80011	80000	80000	80010	80000	80000	240030	1360057	320000	240010	20	80000	80000	20	160000	160000	80001	80000	80000	10
160024	80045	240011	80011	80000	80000	80010	80000	80000	240030	1360057	320000	240010	20	80000	80000	20	160000	160000	80001	80000	80000	10
160024	80045	240011	80011	80000	80000	80010	80000	80000	240030	1360057	320000	240010	20	80000	80000	20	160000	160000	80001	80000	80000	10
160024	80045	240011	80011	80000	80000	80010	80000	80032	240138	1361039	320146	240114	20	80036	80036	20	160000	160000	80001	80000	80000	10
160024	80045	240011	80011	80000	80000	80010	80000	80000	240030	1360057	320000	240010	20	80000	80000	20	160000	160000	80001	80000	80000	10
160024	80045	240011	80011	80000	80000	80010	80000	80000	240030	1360057	320000	240010	20	80000	80000	20	160000	160000	80001	80000	80000	10
160025	80154	240097	80045	80034	80018	80046	80036	80000	240030	1360057	320000	240010	20	80000	80000	20	160000	160000	80001	80000	80000	10
160024	80045	240011	80011	80000	80000	80010	80000	80000	240030	1360057	320000	240010	20	80000	80000	20	160000	160000	80001	80000	80000	10
160024	80045	240011	80011	80000	80000	80010	80000	80000	240030	1360057	320000	240010	20	80000	80000	20	160000	160000	80001	80000	80000	10

STP (pre-index, S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 3->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations