Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
stp q0, q1, [x6, #0x10] nop ; nop ; nop ; nop ; nop ; nop ; nop
mov x0, 0
(no loop instructions)
Retires (minus 7 nops): 2.000
Issues: 2.000
Integer unit issues: 0.001
Load/store unit issues: 2.000
SIMD/FP unit issues: 0.000
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch ldst uop (58) | simd uops in schedulers (5a) | dispatch uop (78) | map ldst uop (7d) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) |
9005 | 4145 | 2019 | 1 | 2018 | 2000 | 8534 | 2000 | 2000 | 4000 | 1 | 2000 |
9004 | 2413 | 2001 | 1 | 2000 | 2000 | 9124 | 2000 | 2000 | 4000 | 1 | 2000 |
9004 | 2504 | 2033 | 1 | 2032 | 2000 | 8534 | 2000 | 2000 | 4000 | 1 | 2000 |
9004 | 2301 | 2001 | 1 | 2000 | 2000 | 8534 | 2000 | 2000 | 4000 | 1 | 2000 |
9004 | 2301 | 2001 | 1 | 2000 | 2000 | 8534 | 2000 | 2000 | 4000 | 1 | 2000 |
9004 | 2301 | 2001 | 1 | 2000 | 2000 | 8534 | 2000 | 2000 | 4000 | 1 | 2000 |
9004 | 2301 | 2001 | 1 | 2000 | 2000 | 8534 | 2000 | 2000 | 4000 | 1 | 2000 |
9004 | 2301 | 2001 | 1 | 2000 | 2000 | 8534 | 2000 | 2000 | 4000 | 1 | 2000 |
9004 | 2301 | 2001 | 1 | 2000 | 2000 | 8534 | 2000 | 2000 | 4000 | 1 | 2000 |
9004 | 2301 | 2001 | 1 | 2000 | 2000 | 9240 | 2000 | 2000 | 4000 | 1 | 2000 |
Count: 8
Code:
stp q0, q1, [x6, #0x10] stp q0, q1, [x6, #0x10] stp q0, q1, [x6, #0x10] stp q0, q1, [x6, #0x10] stp q0, q1, [x6, #0x10] stp q0, q1, [x6, #0x10] stp q0, q1, [x6, #0x10] stp q0, q1, [x6, #0x10]
mov x7, x6 mov x8, x6 mov x9, x6 mov x10, x6 mov x11, x6 mov x12, x6 mov x13, x6
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 2.0006
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) |
160205 | 160152 | 160119 | 101 | 160018 | 100 | 160001 | 300 | 2719974 | 160101 | 200 | 160008 | 200 | 320016 | 1 | 160000 | 100 |
160204 | 160047 | 160101 | 101 | 160000 | 100 | 160001 | 300 | 2720046 | 160101 | 200 | 160008 | 200 | 320016 | 1 | 160000 | 100 |
160204 | 160047 | 160101 | 101 | 160000 | 100 | 160001 | 300 | 2720046 | 160101 | 200 | 160008 | 200 | 320016 | 1 | 160000 | 100 |
160204 | 160047 | 160101 | 101 | 160000 | 100 | 160001 | 300 | 2720046 | 160101 | 200 | 160008 | 200 | 320016 | 1 | 160000 | 100 |
160204 | 160047 | 160101 | 101 | 160000 | 100 | 160001 | 300 | 2720046 | 160101 | 200 | 160008 | 200 | 320016 | 1 | 160000 | 100 |
160204 | 160047 | 160101 | 101 | 160000 | 100 | 160001 | 300 | 2720046 | 160101 | 200 | 160008 | 200 | 320016 | 1 | 160000 | 100 |
160204 | 160047 | 160101 | 101 | 160000 | 100 | 160001 | 300 | 2720046 | 160101 | 200 | 160008 | 200 | 320016 | 1 | 160000 | 100 |
160204 | 160047 | 160101 | 101 | 160000 | 100 | 160001 | 300 | 2720046 | 160101 | 200 | 160008 | 200 | 320016 | 1 | 160000 | 100 |
160204 | 160047 | 160101 | 101 | 160000 | 100 | 160001 | 300 | 2720046 | 160101 | 200 | 160008 | 200 | 320016 | 1 | 160000 | 100 |
160204 | 160047 | 160101 | 101 | 160000 | 100 | 160001 | 300 | 2720046 | 160101 | 200 | 160008 | 200 | 320016 | 1 | 160000 | 100 |
Result (median cycles for code divided by count): 2.0006
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) |
160025 | 160163 | 160029 | 11 | 160018 | 10 | 160001 | 30 | 2720010 | 160011 | 20 | 160008 | 20 | 320000 | 1 | 160000 | 10 |
160024 | 160047 | 160011 | 11 | 160000 | 10 | 160000 | 30 | 2720043 | 160010 | 20 | 160000 | 20 | 320000 | 1 | 160000 | 10 |
160024 | 160047 | 160011 | 11 | 160000 | 10 | 160000 | 30 | 2720043 | 160010 | 20 | 160000 | 20 | 320000 | 1 | 160000 | 10 |
160024 | 160047 | 160011 | 11 | 160000 | 10 | 160000 | 30 | 2720043 | 160010 | 20 | 160000 | 20 | 320000 | 1 | 160000 | 10 |
160024 | 160047 | 160011 | 11 | 160000 | 10 | 160000 | 30 | 2720043 | 160010 | 20 | 160000 | 20 | 320000 | 1 | 160000 | 10 |
160025 | 160075 | 160028 | 11 | 160017 | 10 | 160000 | 30 | 2720043 | 160010 | 20 | 160000 | 20 | 320000 | 1 | 160000 | 10 |
160024 | 160047 | 160011 | 11 | 160000 | 10 | 160000 | 30 | 2720043 | 160010 | 20 | 160000 | 20 | 320000 | 1 | 160000 | 10 |
160024 | 160047 | 160011 | 11 | 160000 | 10 | 160000 | 30 | 2720043 | 160010 | 20 | 160000 | 20 | 320000 | 1 | 160000 | 10 |
160024 | 160047 | 160011 | 11 | 160000 | 10 | 160000 | 30 | 2720043 | 160010 | 20 | 160000 | 20 | 320000 | 1 | 160000 | 10 |
160024 | 160047 | 160011 | 11 | 160000 | 10 | 160034 | 30 | 2720156 | 160044 | 20 | 160048 | 20 | 320000 | 1 | 160000 | 10 |