Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

STR (D)

Test 1: uops

Code:

  str d0, [x6]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	1156	1019	1	1018	1000	17079	1000	1000	2000	1	1000
1004	1047	1001	1	1000	1000	16883	1000	1000	2000	1	1000
1004	1039	1001	1	1000	1000	16883	1000	1000	2000	1	1000
1004	1047	1001	1	1000	1000	16883	1000	1000	2000	1	1000
1004	1039	1001	1	1000	1000	16883	1000	1000	2000	1	1000
1004	1039	1001	1	1000	1000	16883	1000	1000	2000	1	1000
1004	1039	1001	1	1000	1000	16883	1000	1000	2000	1	1000
1004	1039	1001	1	1000	1000	16937	1000	1000	2000	1	1000
1004	1039	1001	1	1000	1000	16883	1000	1000	2000	1	1000
1004	1039	1001	1	1000	1000	16883	1000	1000	2000	1	1000

Test 2: throughput

Count: 8

Code:

  str d0, [x6]
  str d0, [x6]
  str d0, [x6]
  str d0, [x6]
  str d0, [x6]
  str d0, [x6]
  str d0, [x6]
  str d0, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80204	80068	80101	101	80000	100	80001	300	1359992	0	80101	200	80008	0	200	160016	1	80000	100
80204	80047	80101	101	80000	100	80001	300	1359886	0	80101	200	80008	0	200	160016	1	80000	100
80204	80039	80101	101	80000	100	80001	300	1359886	0	80101	200	80008	0	200	160016	1	80000	100
80204	80039	80101	101	80000	100	80001	300	1359886	0	80101	200	80008	0	200	160016	1	80000	100
80204	80039	80101	101	80000	100	80001	300	1359886	0	80101	200	80008	0	200	160016	1	80000	100
80204	80039	80101	101	80000	100	80001	300	1359886	0	80101	200	80008	0	200	160016	1	80000	100
80205	80067	80118	101	80017	100	80001	300	1359886	0	80101	200	80008	0	200	160016	1	80000	100
95248	116200	97150	9806	87344	10722	80001	300	1359886	0	80101	200	80008	0	200	160016	1	80000	100
80204	80046	80101	101	80000	100	80076	300	1362193	0	80176	200	80093	0	200	160016	1	80000	100
80204	80237	80137	101	80036	100	80001	300	1360012	0	80101	200	80008	0	200	160016	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80025	80147	80029	11	80018	10	80037	30	1360294	80047	20	80052	20	160016	1	80000	10
80024	80037	80011	11	80000	10	80000	30	1359847	80010	20	80000	20	160000	1	80000	10
80024	80038	80011	11	80000	10	80000	30	1359847	80010	20	80000	20	160000	1	80000	10
80024	80037	80011	11	80000	10	80000	30	1359847	80010	20	80000	20	160184	1	80000	10
80024	80067	80011	11	80000	10	80000	30	1360007	80010	20	80000	20	160000	1	80000	10
80024	80037	80011	11	80000	10	80000	30	1359847	80010	20	80000	20	160000	1	80000	10
80024	80037	80011	11	80000	10	80000	30	1359847	80010	20	80000	20	160000	1	80000	10
80024	80037	80011	11	80000	10	80000	30	1359847	80010	20	80000	20	160000	1	80000	10
80024	80037	80011	11	80000	10	80000	30	1359847	80010	20	80000	20	160000	1	80000	10
80024	80037	80011	11	80000	10	80000	30	1359847	80010	20	80000	20	160000	1	80000	10