Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

STR (S)

Test 1: uops

Code:

  str s0, [x6]
  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch ldst uop (58)simd uops in schedulers (5a)dispatch uop (78)map ldst uop (7d)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)
1005115610191101810001704310001000200011000
1004104710011100010001704310001000200011000
1004104710011100010001704310001000200011000
1004104710011100010001704310001000200011000
1004104710011100010001704310001000200011000
1004104710011100010001704310001000200011000
1004104710011100010001704310001000200011000
1004104710011100010001704310001000200011000
1004104710011100010001704310001000200011000
1004104710011100010001704310001000200011000

Test 2: throughput

Count: 8

Code:

  str s0, [x6]
  str s0, [x6]
  str s0, [x6]
  str s0, [x6]
  str s0, [x6]
  str s0, [x6]
  str s0, [x6]
  str s0, [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
80205806348011910108001810008000130013600108010120080008200160016180000100
80204800478010110108000010008000130013598868010120080008200160016180000100
80204800398010110108000010008000130013598868010120080008200160098180000100
80204800398010110108000010008000130013598868010120080008200160016180000100
80204800398010110108000010008000130013598868010120080008200160016180000100
80204800398010110108000010008000130013598868010120080008200160016180000100
80204800398010110108000010008000130013598868010120080008200160016180000100
80204800398010110108000010008000130013598868010120080008200160104180000100
80204800398010110108000010008000130013598868010120080008200160016180000100
80204800398010110108000010008000130013598868010120080008200160104180000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
800258016080029118001810800003013599718001020800002016000018000010
800248058880065118005410800003013600078001020800002016000018000010
800248004580011118000010800003013600078001020800002016016418000010
800248004580011118000010800003013600078001020800002016000018000010
800248004580011118000010800723013667578008220800822016000018000010
800248039680029118001810800003013606918001020800002016000018000010
800248004580011118000010800003013600078001020800002016000018000010
800248004580011118000010800003013600078001020800002016010418000010
800248004580011118000010800003013600078001020800002016000018000010
800248004580011118000010800003013600078001020800002016000018000010