Icestorm: STR (post-index, D) measurements

Code:

  str d0, [x6], #0x10

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	1633	2059	1041	1018	1040	1000	4645	18313	2000	1000	2000	1001	1000
1004	1119	2001	1001	1000	1000	1000	4801	19081	2000	1000	2000	1001	1000
1004	1154	2001	1001	1000	1000	1000	4805	18781	2000	1000	2000	1001	1000
1004	1212	2001	1001	1000	1000	1000	4801	19411	2000	1000	2000	1001	1000
1004	1118	2001	1001	1000	1000	1000	4801	19189	2000	1000	2000	1001	1000
1004	1143	2001	1001	1000	1000	1000	4801	19405	2000	1000	2000	1001	1000
1004	1180	2001	1001	1000	1000	1000	4801	19963	2000	1000	2000	1001	1000
1004	1190	2001	1001	1000	1000	1000	4801	18811	2000	1000	2000	1001	1000
1004	1148	2001	1001	1000	1000	1000	4801	19945	2000	1000	2000	1001	1000
1004	1133	2001	1001	1000	1000	1000	4801	18559	2000	1000	2000	1001	1000

Test 2: Latency 3->3

Code:

  str d0, [x6], #0x10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.1344

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
10214	14665	20695	10515	10180	10516	10003	44314	192507	20109	200	10010	200	20020	0	10007	10000	0	100
10204	11225	20105	10105	10000	10106	10004	43638	191672	20112	200	10012	200	20016	0	10004	10000	0	100
10204	11276	20104	10104	10000	10104	10002	43620	191717	20106	200	10008	200	20016	0	10004	10000	0	100
10204	11245	20105	10105	10000	10108	10002	43629	192067	20106	200	10008	200	20016	0	10004	10000	0	100
10204	11220	20104	10104	10000	10104	10002	43621	192319	20106	200	10008	200	20024	0	10005	10000	0	100
10204	11313	20104	10104	10000	10104	10002	43622	192465	20106	200	10008	200	20016	0	10004	10000	0	100
10204	11351	20101	10101	10000	10104	10002	43627	193171	20106	200	10008	200	20024	0	10005	10000	0	100
10204	11263	20105	10105	10000	10108	10036	45124	195903	20179	200	10051	200	20024	0	10005	10000	0	100
10204	11192	20103	10103	10000	10104	10002	43617	203125	20106	200	10008	200	20012	0	10003	10000	0	100
10204	11610	20101	10101	10000	10104	10003	44338	194208	20109	200	10010	200	20016	0	10001	10000	0	100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.1324

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10034	14259	20611	10431	10180	10432	10003	43805	194434	20019	20	10010	20	20000	10001	10000	10
10024	11377	20011	10011	10000	10010	10000	43118	193951	20010	20	10000	20	20000	10001	10000	10
10024	11365	20011	10011	10000	10010	10000	43114	193681	20010	20	10000	20	20000	10001	10000	10
10024	11360	20011	10011	10000	10010	10000	43119	193861	20010	20	10000	20	20088	10033	10000	10
10024	11391	20011	10011	10000	10010	10000	43113	193915	20010	20	10000	20	20000	10001	10000	10
10024	11384	20011	10011	10000	10010	10000	43118	193771	20010	20	10000	20	20000	10001	10000	10
10024	11397	20011	10011	10000	10010	10000	43116	193753	20010	20	10000	20	20000	10001	10000	10
10024	11369	20011	10011	10000	10010	10000	43117	193897	20010	20	10000	20	20000	10001	10000	10
10024	11385	20011	10011	10000	10010	10000	43121	193735	20010	20	10000	20	20000	10001	10000	10
10024	11359	20011	10011	10000	10010	10000	43119	194185	20010	20	10000	20	20000	10001	10000	10

Test 3: throughput

Count: 8

Code:

  str d0, [x6], #0x10
  str d0, [x7], #0x10
  str d0, [x8], #0x10
  str d0, [x9], #0x10
  str d0, [x10], #0x10
  str d0, [x11], #0x10
  str d0, [x12], #0x10
  str d0, [x13], #0x10

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80214	82111	160692	80512	80180	80511	80038	240432	1361260	0	160182	200	80048	0	200	160016	0	80005	80000	0	100
80204	80056	160105	80105	80000	80104	80002	240312	1360051	0	160106	200	80008	0	200	160016	0	80005	80000	0	100
80204	80048	160105	80105	80000	80104	80002	240312	1360051	0	160106	200	80008	0	200	160016	0	80005	80000	0	100
80204	80056	160105	80105	80000	80104	80035	240423	1360737	0	160178	202	80046	0	27658	174947	375	91054	86442	149	14706
80204	80078	160105	80105	80000	80104	80002	240312	1360607	0	160106	200	80008	0	200	160016	0	80005	80000	0	100
80204	80048	160105	80105	80000	80104	80002	240312	1360051	0	160106	200	80008	0	200	160016	0	80005	80000	0	100
80204	80048	160105	80105	80000	80104	80002	240312	1360051	0	160106	200	80008	0	200	160016	0	80005	80000	0	100
80204	80048	160105	80105	80000	80104	80002	240312	1360051	0	160106	200	80008	0	200	160016	0	80005	80000	0	100
80204	80048	160105	80105	80000	80104	80002	240312	1360051	0	160106	200	80008	0	200	160016	0	80005	80000	0	100
80204	80048	160105	80105	80000	80104	80002	240312	1360051	0	160106	200	80008	0	200	160016	0	80005	80000	0	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0012

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80034	82241	160612	80432	80180	80432	80036	240155	1360994	160088	20	80050	20	160016	80005	80000	10
80024	80056	160011	80011	80000	80010	80000	240030	1360205	160010	20	80000	20	160000	80001	80000	10
80024	80056	160011	80011	80000	80010	80000	240030	1360205	160010	20	80000	20	160000	80001	80000	10
80024	80056	160011	80011	80000	80010	80000	240030	1360205	160010	20	80000	20	160000	80001	80000	10
80024	80056	160011	80011	80000	80010	80000	240030	1360205	160010	20	80000	20	160000	80001	80000	10
80024	80056	160011	80011	80000	80010	80000	240030	1360205	160010	20	80000	20	160000	80001	80000	10
80024	80056	160011	80011	80000	80010	80000	240030	1360205	160010	20	80000	20	160000	80001	80000	10
80024	80056	160011	80011	80000	80010	80000	240030	1360205	160010	20	80000	20	160000	80001	80000	10
80024	80056	160011	80011	80000	80010	80000	240030	1360205	160010	20	80000	20	160000	80001	80000	10
80024	80056	160011	80011	80000	80010	80000	240030	1360205	160010	20	80000	20	160096	80037	80000	10

STR (post-index, D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 3->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations