Icestorm: STR (post-index, S) measurements

Code:

  str s0, [x6], #0x10

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	1408	2059	1041	1018	1040	1000	5213	18176	2000	1000	2000	1001	1000
1004	1167	2001	1001	1000	1000	1000	4813	18811	2000	1000	2000	1001	1000
1004	1145	2001	1001	1000	1000	1000	4813	18775	2000	1000	2000	1001	1000
1004	1112	2001	1001	1000	1000	1000	4813	18523	2000	1000	2000	1001	1000
1004	1133	2001	1001	1000	1000	1000	4813	18883	2000	1000	2000	1001	1000
1004	1162	2001	1001	1000	1000	1000	4813	19261	2000	1000	2000	1001	1000
1004	1166	2001	1001	1000	1000	1000	4813	18919	2000	1000	2000	1001	1000
1004	1184	2001	1001	1000	1000	1000	4805	18883	2000	1000	2000	1001	1000
1004	1219	2001	1001	1000	1000	1000	4785	18757	2000	1000	2000	1001	1000
1004	1119	2001	1001	1000	1000	1000	4785	19027	2000	1000	2000	1001	1000

Test 2: Latency 3->3

Code:

  str s0, [x6], #0x10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.1328

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10214	14627	20698	10518	10180	10518	10005	44411	192254	20114	200	10010	200	20016	10004	10000	100
10204	11276	20104	10104	10000	10104	10001	43622	192196	20105	200	10008	200	20016	10004	10000	100
10204	11256	20105	10105	10000	10108	10001	43634	191530	20105	200	10008	200	20016	10004	10000	100
10204	11297	20103	10103	10000	10104	10002	43619	192625	20106	200	10008	200	20024	10005	10000	100
10204	11298	20104	10104	10000	10104	10001	43643	191350	20105	200	10008	200	20024	10005	10000	100
10204	11252	20104	10104	10000	10104	10002	43650	192523	20106	200	10008	200	20016	10004	10000	100
10204	11252	20104	10104	10000	10104	10004	43648	190718	20112	200	10012	200	20024	10005	10000	100
10204	11266	20104	10104	10000	10104	10001	43621	192946	20105	200	10008	200	20008	10001	10000	100
10204	11328	20104	10104	10000	10104	10001	43634	192070	20105	200	10008	200	20016	10003	10000	100
10204	11532	20219	10183	10036	10185	10002	43640	190625	20106	200	10008	200	20016	10004	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.1209

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10034	15321	20611	10431	10180	10432	10003	44180	192412	20019	20	10010	20	20000	10001	10000	10
10024	11151	20011	10011	10000	10010	10000	43102	192143	20010	20	10000	20	20000	10001	10000	10
10024	11204	20011	10011	10000	10010	10000	43105	191099	20010	20	10000	20	20000	10001	10000	10
10024	11177	20011	10011	10000	10010	10000	43106	190721	20010	20	10000	20	20000	10001	10000	10
10024	11196	20011	10011	10000	10010	10000	43106	189965	20010	20	10000	20	20000	10001	10000	10
10024	11161	20011	10011	10000	10010	10000	43106	190055	20010	20	10000	20	20000	10001	10000	10
10024	11159	20011	10011	10000	10010	10000	43104	190703	20010	20	10000	20	20000	10001	10000	10
10024	11147	20011	10011	10000	10010	10000	43102	191423	20010	20	10000	20	20000	10001	10000	10
10024	11166	20011	10011	10000	10010	10000	43102	191297	20010	20	10000	20	20000	10001	10000	10
10024	11296	20011	10011	10000	10010	10000	43104	190397	20010	20	10000	20	20000	10001	10000	10

Test 3: throughput

Count: 8

Code:

  str s0, [x6], #0x10
  str s0, [x7], #0x10
  str s0, [x8], #0x10
  str s0, [x9], #0x10
  str s0, [x10], #0x10
  str s0, [x11], #0x10
  str s0, [x12], #0x10
  str s0, [x13], #0x10

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80214	82075	160692	80512	80180	80511	80002	240312	1360211	160106	200	80008	200	160016	80005	80000	100
80204	80056	160105	80105	80000	80104	80002	240312	1360211	160106	200	80008	200	160016	80005	80000	100
80205	80138	160155	80138	80017	80142	80002	240312	1360211	160106	200	80008	200	160016	80005	80000	100
80204	80056	160105	80105	80000	80104	80002	240312	1360211	160106	200	80008	200	160096	80037	80000	100
80204	80056	160105	80105	80000	80104	80002	240312	1360211	160106	200	80008	200	160016	80005	80000	100
80204	80056	160105	80105	80000	80104	80002	240312	1360211	160106	200	80008	200	160016	80005	80000	100
80204	80056	160105	80105	80000	80104	80002	240312	1360391	160106	200	80008	200	160016	80005	80000	100
80204	80056	160105	80105	80000	80104	80002	240312	1360211	160106	200	80008	200	160016	80005	80000	100
80204	80056	160105	80105	80000	80104	80002	240312	1360211	160106	200	80008	200	160096	80040	80000	100
80204	80152	160163	80145	80018	80144	80002	240312	1360211	160106	200	80008	200	160016	80005	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0011

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80034	82318	160612	80432	80180	80432	80002	240042	1360157	160016	20	80008	20	160016	80005	80000	10
80024	80053	160015	80015	80000	80014	80000	240030	1359991	160010	20	80000	20	160000	80001	80000	10
80024	80045	160011	80011	80000	80010	80000	240030	1359991	160010	20	80000	20	160000	80001	80000	10
80024	80045	160011	80011	80000	80010	80000	240030	1359991	160010	20	80000	20	160000	80001	80000	10
80024	80045	160011	80011	80000	80010	80000	240030	1359991	160010	20	80000	20	160000	80001	80000	10
80024	80045	160011	80011	80000	80010	80000	240030	1359991	160010	20	80000	20	160000	80001	80000	10
80024	80045	160011	80011	80000	80010	80000	240030	1359991	160010	20	80000	20	160000	80001	80000	10
80024	80045	160011	80011	80000	80010	80000	240030	1359991	160010	20	80000	20	160000	80001	80000	10
80024	80045	160011	80011	80000	80010	80000	240030	1359991	160010	20	80000	20	160000	80001	80000	10
80025	80110	160064	80047	80017	80050	80000	240030	1360151	160010	20	80000	20	160000	80001	80000	10

STR (post-index, S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 3->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations