Icestorm: STR (pre-index, Q) measurements

Code:

  str q0, [x6, #0x10]!

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	1440	2059	1041	1018	1040	1000	4697	18415	2000	1000	2000	1001	1000
1004	1108	2001	1001	1000	1000	1000	4681	19063	2000	1000	2000	1001	1000
1004	1114	2001	1001	1000	1000	1000	4681	18127	2000	1000	2000	1001	1000
1004	1113	2001	1001	1000	1000	1000	4693	19909	2000	1000	2000	1001	1000
1004	1162	2001	1001	1000	1000	1000	4693	19297	2000	1000	2000	1001	1000
1004	1145	2001	1001	1000	1000	1000	4693	18901	2000	1000	2000	1001	1000
1004	1138	2001	1001	1000	1000	1000	4693	18217	2000	1000	2000	1001	1000
1004	1121	2001	1001	1000	1000	1000	4693	18109	2000	1000	2000	1001	1000
1004	1138	2001	1001	1000	1000	1000	4693	19243	2000	1000	2000	1001	1000
1004	1138	2001	1001	1000	1000	1000	4693	18127	2000	1000	2000	1001	1000

Test 2: Latency 3->3

Code:

  str q0, [x6, #0x10]!

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.1251

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10214	15484	20701	10521	10180	10523	10002	44297	191762	20108	200	10010	200	20020	10003	10000	100
10204	11295	20104	10104	10000	10107	10001	43606	192180	20105	200	10008	200	20016	10004	10000	100
10204	11300	20104	10104	10000	10104	10001	43615	192324	20105	200	10008	200	20016	10003	10000	100
10204	11255	20104	10104	10000	10104	10002	43577	191473	20106	200	10008	200	20016	10003	10000	100
10204	11290	20103	10103	10000	10104	10000	43581	192853	20100	200	10004	200	20016	10004	10000	100
10204	11418	20104	10104	10000	10104	10001	43611	192818	20105	200	10008	200	20016	10003	10000	100
10204	11270	20104	10104	10000	10104	10002	43601	191995	20106	200	10008	200	20016	10004	10000	100
10204	11281	20103	10103	10000	10104	10002	43615	191365	20106	200	10008	200	20016	10003	10000	100
10204	11256	20104	10104	10000	10104	10001	43615	192216	20105	200	10008	200	20016	10003	10000	100
10204	11229	20104	10104	10000	10104	10001	43622	191298	20105	200	10008	200	20016	10003	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.1251

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10034	15922	20609	10429	10180	10430	10003	44110	190676	20019	20	10010	20	20016	10003	10000	10
10024	11307	20013	10013	10000	10016	10001	43104	192290	20015	20	10008	20	20000	10001	10000	10
10024	11237	20011	10011	10000	10010	10000	43094	191675	20010	20	10000	20	20000	10001	10000	10
10024	11193	20011	10011	10000	10010	10000	43088	192017	20010	20	10000	20	20000	10001	10000	10
10024	11243	20011	10011	10000	10010	10000	43094	192359	20010	20	10000	20	20000	10001	10000	10
10024	11260	20011	10011	10000	10010	10000	43090	191081	20010	20	10000	20	20000	10001	10000	10
10024	11286	20011	10011	10000	10010	10000	43093	192125	20010	20	10000	20	20000	10001	10000	10
10024	11248	20011	10011	10000	10010	10000	43090	191459	20010	20	10000	20	20000	10001	10000	10
10024	11242	20011	10011	10000	10010	10000	43089	191297	20010	20	10000	20	20000	10001	10000	10
10024	11241	20011	10011	10000	10010	10000	42942	191999	20010	20	10000	20	20000	10001	10000	10

Test 3: throughput

Count: 8

Code:

  str q0, [x6, #0x10]!
  str q0, [x7, #0x10]!
  str q0, [x8, #0x10]!
  str q0, [x9, #0x10]!
  str q0, [x10, #0x10]!
  str q0, [x11, #0x10]!
  str q0, [x12, #0x10]!
  str q0, [x13, #0x10]!

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0010

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80214	82361	160692	80512	80180	80511	80002	240312	1360648	160106	200	80008	200	160016	80005	80000	100
80204	80083	160105	80105	80000	80104	80035	240419	1361383	160175	200	80048	200	160016	80005	80000	100
80204	80083	160105	80105	80000	80104	80002	240312	1360697	160106	200	80008	200	160016	80005	80000	100
80204	80083	160105	80105	80000	80104	80002	240312	1360697	160106	200	80008	200	160016	80005	80000	100
80204	80083	160105	80105	80000	80104	80002	240312	1360697	160106	200	80008	200	160016	80005	80000	100
80204	80083	160105	80105	80000	80104	80002	240312	1360697	160106	200	80008	200	160016	80005	80000	100
80204	80083	160105	80105	80000	80104	80002	240312	1360697	160106	200	80008	200	160016	80005	80000	100
80204	80083	160105	80105	80000	80104	80002	240312	1360697	160106	200	80008	200	160016	80005	80000	100
80204	80084	160105	80105	80000	80104	80002	240312	1360697	160106	200	80008	200	160016	80005	80000	100
80204	80083	160105	80105	80000	80104	80002	240312	1360697	160106	200	80008	200	160016	80005	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80034	82060	160612	80432	80180	80432	80002	240042	1360147	160016	20	80008	20	160016	80005	80000	10
80024	80056	160011	80011	80000	80010	80000	240030	1360205	160010	20	80000	20	160000	80001	80000	10
80024	80056	160011	80011	80000	80010	80000	240030	1360205	160010	20	80000	20	160000	80001	80000	10
80024	80056	160011	80011	80000	80010	80000	240030	1360205	160010	20	80000	20	160000	80001	80000	10
80024	80056	160011	80011	80000	80010	80000	240030	1360205	160010	20	80000	20	160000	80001	80000	10
80024	80056	160011	80011	80000	80010	80000	240030	1360205	160010	20	80000	20	160000	80001	80000	10
80024	80056	160011	80011	80000	80010	80035	240149	1360807	160085	20	80048	20	160000	80001	80000	10
80024	80056	160011	80011	80000	80010	80000	240030	1360205	160010	20	80000	20	160000	80001	80000	10
80024	80056	160011	80011	80000	80010	80000	240030	1360205	160010	20	80000	20	160000	80001	80000	10
80024	80056	160011	80011	80000	80010	80000	240030	1360205	160010	20	80000	20	160000	80001	80000	10

STR (pre-index, Q)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 3->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations