Icestorm: STR (pre-index, S) measurements

Code:

  str s0, [x6, #0x10]!

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	1694	2059	1041	1018	1040	1000	4637	18253	2000	1000	2000	1001	1000
1004	1116	2001	1001	1000	1000	1000	4637	18487	2000	1000	2000	1001	1000
1004	1113	2001	1001	1000	1000	1000	4637	18145	2000	1000	2000	1001	1000
1004	1105	2001	1001	1000	1000	1000	4637	18019	2000	1000	2000	1001	1000
1004	1110	2001	1001	1000	1000	1000	4637	18721	2000	1000	2000	1001	1000
1004	1137	2001	1001	1000	1000	1000	4637	18433	2000	1000	2000	1001	1000
1004	1104	2001	1001	1000	1000	1000	4637	18391	2000	1000	2000	1001	1000
1004	1115	2001	1001	1000	1000	1000	4637	18469	2000	1000	2000	1001	1000
1004	1135	2001	1001	1000	1000	1000	4637	18037	2000	1000	2000	1001	1000
1004	1128	2001	1001	1000	1000	1000	4641	19404	2000	1000	2000	1001	1000

Test 2: Latency 3->3

Code:

  str s0, [x6, #0x10]!

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.1386

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10214	16823	20703	10523	0	10180	10524	0	10003	44433	192994	20109	200	10010	200	20020	10005	10000	100
10204	11394	20104	10104	0	10000	10104	0	10003	43704	194233	20109	200	10010	200	20016	10004	10000	100
10204	11438	20103	10103	0	10000	10104	0	10001	43489	193953	20105	200	10008	200	20016	10004	10000	100
10204	11375	20104	10104	0	10000	10104	0	10001	43479	194270	20105	200	10008	200	20016	10004	10000	100
10204	11402	20104	10104	0	10000	10104	0	10001	43491	194404	20105	200	10008	200	20016	10004	10000	100
10204	11349	20104	10104	0	10000	10104	0	10001	43510	193062	20105	200	10008	200	20016	10004	10000	100
10204	11547	20161	10143	0	10018	10146	0	10000	43473	193973	20100	200	10004	200	20016	10004	10000	100
10204	11411	20104	10104	0	10000	10104	0	10002	43492	194246	20106	200	10008	200	20016	10004	10000	100
10204	11386	20101	10101	0	10000	10103	0	10002	43504	194120	20106	200	10008	200	20016	10004	10000	100
10204	11390	20104	10104	0	10000	10104	0	10002	43465	193597	20106	200	10008	200	20016	10003	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.1244

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10034	16065	20611	10431	10180	10432	10003	44596	192322	20019	20	10010	20	20000	10001	10000	10
10024	11257	20011	10011	10000	10010	10000	43096	193285	20010	20	10000	20	20000	10001	10000	10
10024	11270	20011	10011	10000	10010	10000	43094	191809	20010	20	10000	20	20000	10001	10000	10
10024	11212	20011	10011	10000	10010	10000	43094	192115	20010	20	10000	20	20000	10001	10000	10
10024	11221	20011	10011	10000	10010	10000	43094	192457	20010	20	10000	20	20000	10001	10000	10
10024	11212	20011	10011	10000	10010	10000	43094	191683	20010	20	10000	20	20000	10001	10000	10
10024	11263	20011	10011	10000	10010	10000	43094	191539	20010	20	10000	20	20000	10001	10000	10
10024	11258	20011	10011	10000	10010	10000	43095	192565	20010	20	10000	20	20000	10001	10000	10
10024	11207	20011	10011	10000	10010	10000	43094	191701	20010	20	10000	20	20000	10001	10000	10
10024	11198	20011	10011	10000	10010	10000	43094	191989	20010	20	10000	20	20000	10001	10000	10

Test 3: throughput

Count: 8

Code:

  str s0, [x6, #0x10]!
  str s0, [x7, #0x10]!
  str s0, [x8, #0x10]!
  str s0, [x9, #0x10]!
  str s0, [x10, #0x10]!
  str s0, [x11, #0x10]!
  str s0, [x12, #0x10]!
  str s0, [x13, #0x10]!

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80214	82040	160692	80512	0	80180	80511	0	80002	240312	1360108	160106	200	80008	200	160096	80037	80000	100
80204	80053	160105	80105	0	80000	80104	0	80002	240312	1360157	160106	200	80008	200	160016	80005	80000	100
84864	110245	164054	82528	47	81479	82346	33	80002	240312	1360105	160106	200	80008	200	160016	80005	80000	100
80204	80053	160105	80105	0	80000	80104	0	80002	240312	1360157	160106	200	80008	200	160016	80005	80000	100
80204	80053	160105	80105	0	80000	80104	0	80002	240312	1360157	160106	200	80008	200	160016	80005	80000	100
80204	80053	160105	80105	0	80000	80104	0	80002	240312	1360157	160106	200	80008	200	160016	80005	80000	100
80204	80065	160105	80105	0	80000	80104	0	80002	240312	1360157	160106	200	80008	200	160016	80005	80000	100
80204	80053	160105	80105	0	80000	80104	0	80002	240312	1360157	160106	200	80008	200	160016	80005	80000	100
80204	80053	160105	80105	0	80000	80104	0	80035	240419	1360985	160175	200	80048	200	160100	80038	80000	100
80204	80053	160105	80105	0	80000	80104	0	80002	240312	1360157	160106	200	80008	200	160096	80037	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0011

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80034	82071	160612	80432	80180	80432	80003	240048	1360652	160019	20	80010	20	160016	80005	80000	0	10
80024	80083	160011	80011	80000	80010	80000	240030	1360691	160010	20	80000	20	160000	80001	80000	0	10
80024	80083	160011	80011	80000	80010	80000	240030	1360691	160010	20	80000	20	160000	80001	80000	0	10
80024	80083	160011	80011	80000	80010	80000	240030	1360691	160010	20	80000	20	160000	80001	80000	0	10
80024	80083	160011	80011	80000	80010	80002	240042	1363163	160016	20	80008	20	160000	80001	80000	0	10
80024	80197	160011	80011	80000	80010	80000	240030	1362743	160010	20	80000	20	160000	80001	80000	0	10
80024	80197	160011	80011	80000	80010	80000	240030	1362743	160010	20	80000	20	160000	80001	80000	0	10
80024	80197	160011	80011	80000	80010	80002	240042	1360697	160016	20	80008	20	160000	80001	80000	0	10
80024	80083	160011	80011	80000	80010	80000	240030	1360691	160010	20	80000	20	160000	80001	80000	0	10
80024	80083	160011	80011	80000	80010	80000	240030	1360691	160010	20	80000	20	160096	80037	80000	0	10

STR (pre-index, S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 3->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations