Icestorm: STR (register, lsl, D) measurements

Code:

  str d0, [x6, x7, lsl #3]

Initialization

  mov x0, 0
  mov x7, 8

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	1150	1019	1	1018	1000	17043	1000	1000	3000	1	1000
1004	1047	1001	1	1000	1000	17043	1000	1000	3000	1	1000
1004	1047	1001	1	1000	1000	17043	1000	1000	3000	1	1000
1004	1047	1001	1	1000	1000	17043	1000	1000	3000	1	1000
1004	1047	1001	1	1000	1000	17043	1000	1000	3000	1	1000
1004	1047	1001	1	1000	1000	17043	1000	1000	3000	1	1000
1004	1047	1001	1	1000	1000	17043	1000	1000	3000	1	1000
1004	1047	1001	1	1000	1000	17043	1000	1000	3000	1	1000
1004	1047	1001	1	1000	1000	17043	1000	1000	3000	1	1000
1004	1047	1001	1	1000	1000	17043	1000	1000	3000	1	1000

Count: 8

Code:

  str d0, [x6, x7, lsl #3]
  str d0, [x6, x7, lsl #3]
  str d0, [x6, x7, lsl #3]
  str d0, [x6, x7, lsl #3]
  str d0, [x6, x7, lsl #3]
  str d0, [x6, x7, lsl #3]
  str d0, [x6, x7, lsl #3]
  str d0, [x6, x7, lsl #3]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80205	80147	80119	101	0	80018	100	0	80001	300	1359974	80101	200	80008	200	240024	1	80000	100
91677	113941	90208	6250	210	83748	5887	203	80001	300	1360172	80101	200	80008	200	240156	1	80000	100
80204	80047	80101	101	0	80000	100	0	80001	300	1360046	80101	200	80008	200	240024	1	80000	100
80204	80047	80101	101	0	80000	100	0	80001	300	1360046	80101	200	80008	200	240024	1	80000	100
80204	80047	80101	101	0	80000	100	0	80001	300	1360046	80101	200	80008	200	240156	1	80000	100
80204	80088	80101	101	0	80000	100	0	80001	300	1360046	80101	200	80008	200	240024	1	80000	100
80204	80239	80137	101	0	80036	100	0	80001	300	1360082	80101	200	80008	200	240024	1	80000	100
80204	80047	80101	101	0	80000	100	0	80001	300	1360046	80101	200	80008	200	240024	1	80000	100
80204	80047	80101	101	0	80000	100	0	80037	300	1360168	80137	200	80052	200	240024	1	80000	100
80204	80047	80101	101	0	80000	100	0	80001	300	1360046	80101	200	80008	200	240024	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80025	80154	80029	11	80018	10	80001	30	1359974	80011	20	80008	20	240000	1	80000	10
80024	80045	80011	11	80000	10	80000	30	1360007	80010	20	80000	20	240000	1	80000	10
80024	80045	80011	11	80000	10	80000	30	1360007	80010	20	80000	20	240000	1	80000	10
80025	80073	80028	11	80017	10	80000	30	1360007	80010	20	80000	20	240000	1	80000	10
80024	80045	80011	11	80000	10	80000	30	1360007	80010	20	80000	20	240000	1	80000	10
80024	80045	80011	11	80000	10	80000	30	1360007	80010	20	80000	20	240000	1	80000	10
80024	80045	80011	11	80000	10	80000	30	1360007	80010	20	80000	20	240000	1	80000	10
80025	80073	80028	11	80017	10	80000	30	1360025	80010	20	80000	20	240024	1	80000	10
80024	80143	80029	11	80018	10	80108	30	1363301	80118	20	80123	20	240000	1	80000	10
80024	80047	80011	11	80000	10	80000	30	1360043	80010	20	80000	20	240000	1	80000	10

STR (register, lsl, D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations