Icestorm: STR (register, lsl, Q) measurements

Code:

  str q0, [x6, x7, lsl #4]

Initialization

  mov x0, 0
  mov x7, 8

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
2006	1216	2051	1033	1018	1032	1000	3000	17067	2000	1000	1000	1000	3000	1001	1000	1000
2004	1048	2001	1001	1000	1000	1000	3000	17067	2000	1000	1000	1000	3000	1001	1000	1000
2004	1048	2001	1001	1000	1000	1000	3000	17067	2000	1000	1000	1000	3000	1001	1000	1000
2004	1048	2001	1001	1000	1000	1000	3000	17067	2000	1000	1000	1000	3000	1001	1000	1000
2004	1048	2001	1001	1000	1000	1000	3000	17067	2000	1000	1000	1000	3000	1001	1000	1000
2004	1048	2001	1001	1000	1000	1000	3000	17067	2000	1000	1000	1000	3000	1001	1000	1000
2004	1048	2001	1001	1000	1000	1000	3000	17067	2000	1000	1000	1000	3000	1001	1000	1000
2004	1048	2001	1001	1000	1000	1000	3000	17067	2000	1000	1000	1000	3000	1001	1000	1000
2004	1048	2001	1001	1000	1000	1000	3000	17067	2000	1000	1000	1000	3000	1001	1000	1000
2004	1048	2001	1001	1000	1000	1000	3000	17067	2000	1000	1000	1000	3000	1001	1000	1000

Count: 8

Code:

  str q0, [x6, x7, lsl #4]
  str q0, [x6, x7, lsl #4]
  str q0, [x6, x7, lsl #4]
  str q0, [x6, x7, lsl #4]
  str q0, [x6, x7, lsl #4]
  str q0, [x6, x7, lsl #4]
  str q0, [x6, x7, lsl #4]
  str q0, [x6, x7, lsl #4]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160206	80216	160155	80137	80018	80138	80001	240318	1359998	0	160107	80206	80006	0	80206	240018	80005	80000	80100
160204	80047	160105	80105	80000	80106	80001	240318	1359998	0	160107	80206	80006	0	80206	240018	80005	80000	80100
160204	80046	160105	80105	80000	80106	80001	240318	1360034	0	160107	80206	80006	0	80206	240018	80005	80000	80100
160204	80046	160105	80105	80000	80106	80001	240318	1360034	0	160107	80206	80006	0	80206	240018	80005	80000	80100
160204	80046	160105	80105	80000	80106	80001	240318	1360034	0	160107	80206	80006	0	80206	240018	80005	80000	80100
160204	80046	160105	80105	80000	80106	80001	240318	1360034	0	160107	80206	80006	0	80206	240018	80005	80000	80100
160204	80046	160105	80105	80000	80106	80001	240318	1360034	0	160107	80206	80006	0	80206	240018	80005	80000	80100
160204	80046	160105	80105	80000	80106	80001	240318	1360034	0	160107	80206	80006	0	80206	240018	80005	80000	80100
160204	80046	160105	80105	80000	80106	80001	240318	1360034	0	160107	80206	80006	0	80206	240018	80005	80000	80100
160204	80046	160105	80105	80000	80106	80001	240318	1360034	0	160107	80206	80006	0	80206	240018	80005	80000	80100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160026	80245	160065	80047	80018	80048	80001	240048	1359886	160017	80026	80006	80026	240018	80005	80000	80010
160024	80040	160015	80015	80000	80016	80001	240048	1360392	160017	80026	80006	80020	240000	80001	80000	80010
160024	80040	160011	80011	80000	80010	80000	240030	1359919	160010	80020	80000	80020	240000	80001	80000	80010
160024	80040	160011	80011	80000	80010	80030	240120	1361078	160070	80050	80030	80020	240000	80001	80000	80010
160024	80040	160011	80011	80000	80010	80000	240030	1359919	160010	80020	80000	80020	240000	80001	80000	80010
160024	80040	160011	80011	80000	80010	80000	240030	1359919	160010	80020	80000	80020	240000	80001	80000	80010
160024	80040	160011	80011	80000	80010	80000	240030	1359919	160010	80020	80000	80020	240000	80001	80000	80010
160024	80040	160011	80011	80000	80010	80000	240030	1359919	160010	80020	80000	80020	240000	80001	80000	80010
160024	80040	160011	80011	80000	80010	80000	240030	1359919	160010	80020	80000	80020	240000	80001	80000	80010
160024	80040	160011	80011	80000	80010	80000	240030	1359919	160010	80020	80000	80020	240000	80001	80000	80010

STR (register, lsl, Q)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations