Icestorm: STR (register, sxtw, Q) measurements

Code:

  str q0, [x6, w7, sxtw]

Initialization

  mov x0, 0
  mov x7, 8

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	1494	1019	1	1018	1000	16883	1000	1000	3000	1	1000
1004	1039	1001	1	1000	1000	16883	1000	1000	3000	1	1000
1004	1039	1001	1	1000	1000	16883	1000	1000	3000	1	1000
1004	1039	1001	1	1000	1000	16883	1000	1000	3000	1	1000
1004	1039	1001	1	1000	1000	16883	1000	1000	3000	1	1000
1004	1039	1001	1	1000	1000	16883	1000	1000	3000	1	1000
1004	1039	1001	1	1000	1000	16883	1000	1000	3000	1	1000
1004	1039	1001	1	1000	1000	16883	1000	1000	3000	1	1000
1004	1039	1001	1	1000	1000	16883	1000	1000	3000	1	1000
1004	1039	1001	1	1000	1000	16883	1000	1000	3000	1	1000

Count: 8

Code:

  str q0, [x6, w7, sxtw]
  str q0, [x6, w7, sxtw]
  str q0, [x6, w7, sxtw]
  str q0, [x6, w7, sxtw]
  str q0, [x6, w7, sxtw]
  str q0, [x6, w7, sxtw]
  str q0, [x6, w7, sxtw]
  str q0, [x6, w7, sxtw]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80205	80377	80119	101	0	80018	100	0	80001	300	1359974	0	80101	200	80008	0	200	240024	1	80000	100
80205	80073	80118	101	0	80017	100	0	80001	300	1359778	0	80101	200	80008	0	200	240024	1	80000	100
80204	80037	80101	101	0	80000	100	0	80001	300	1359850	0	80101	200	80008	0	200	240024	1	80000	100
80204	80037	80101	101	0	80000	100	0	80001	300	1359850	0	80101	200	80008	0	200	240024	1	80000	100
80204	80037	80101	101	0	80000	100	0	80037	300	1360134	0	80137	200	80052	0	200	240024	1	80000	100
80204	80037	80101	101	0	80000	100	0	80001	300	1359850	0	80101	200	80008	0	200	240024	1	80000	100
80204	80037	80101	101	0	80000	100	0	80001	300	1359850	0	80101	200	80008	0	200	240024	1	80000	100
80204	80037	80101	101	0	80000	100	0	80001	300	1359850	0	80101	200	80008	0	200	240024	1	80000	100
80205	80066	80118	101	0	80017	100	0	80001	300	1359868	0	80101	200	80008	0	200	240024	1	80000	100
80204	80037	80101	101	0	80000	100	0	80001	300	1359850	0	80101	200	80008	0	200	240024	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80025	80513	80029	11	80018	10	80001	30	1360010	80011	20	80008	20	240000	1	80000	10
80024	80039	80011	11	80000	10	80034	30	1360149	80044	20	80049	20	240000	1	80000	10
80024	80039	80011	11	80000	10	80000	30	1359883	80010	20	80000	20	240000	1	80000	10
80025	80067	80028	11	80017	10	80000	30	1359883	80010	20	80000	20	240000	1	80000	10
80024	80039	80011	11	80000	10	80034	30	1360005	80044	20	80049	20	240000	1	80000	10
80024	80039	80011	11	80000	10	80001	30	1360322	80011	20	80008	20	240000	1	80000	10
80024	80037	80011	11	80000	10	80000	30	1359847	80010	20	80000	20	240000	1	80000	10
80024	80037	80011	11	80000	10	80000	30	1359847	80010	20	80000	20	240000	1	80000	10
80024	80037	80011	11	80000	10	80000	30	1359847	80010	20	80000	20	240000	1	80000	10
80024	80042	80011	11	80000	10	80000	30	1359973	80010	20	80000	20	240000	1	80000	10

STR (register, sxtw, Q)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations