Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

STR (register, uxtw, D)

Test 1: uops

Code:

  str d0, [x6, w7, uxtw]
  mov x0, 0
  mov x7, 8

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch ldst uop (58)simd uops in schedulers (5a)dispatch uop (78)map ldst uop (7d)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)
1005115010191101810001704310001000300011000
1004104710011100010001704310001000300011000
1004104710011100010001704310001000300011000
1004104710011100010001704310001000300011000
1004104710011100010001704310001000300011000
1004104710011100010001704310001000300011000
1004104710011100010001704310001000300011000
1004104710011100010001704310001000300011000
1004104710011100010001704310001000300011000
1004104710011100010001704310001000300011000

Test 2: throughput

Count: 8

Code:

  str d0, [x6, w7, uxtw]
  str d0, [x6, w7, uxtw]
  str d0, [x6, w7, uxtw]
  str d0, [x6, w7, uxtw]
  str d0, [x6, w7, uxtw]
  str d0, [x6, w7, uxtw]
  str d0, [x6, w7, uxtw]
  str d0, [x6, w7, uxtw]
  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
802058015280119101800181008003730013602768013720080052200240024180000100
802048004780101101800001008000130013598508010120080008200240024180000100
802048003980101101800001008000130013598868010120080008200240024180000100
802048003980101101800001008000130013598868010120080008200240024180000100
802048003980101101800001008000130013598868010120080008200240024180000100
802058006780119102800171028000130013598868010120080008200240024180000100
802048003980101101800001008000130013598868010120080008200240024180000100
802048003980101101800001008000130013598868010120080008200240024180000100
802048003980101101800001008000130013598868010120080008200240024180000100
802048003980101101800001008000130013598868010120080008200240024180000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
800258015480029118001810800013013599748001120800082024000018000010
800248004580011118000010800003013598478001020800002024000018000010
800248003780011118000010800003013598478001020800002024000018000010
800248003780011118000010800003013598478001020800002024000018000010
800248003780011118000010800003013598478001020800002024000018000010
800248003780011118000010800003013598478001020800002024000018000010
800248003780011118000010800003013598478001020800002024000018000010
800258006580028118001710800003013600078001020800002024000018000010
800248003780011118000010800003013598478001020800002024000018000010
800248003780011118000010800003013598478001020800002024000018000010