Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

STR (signed offset, Q)

Test 1: uops

Code:

  str q0, [x6, #0x10]
  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch ldst uop (58)simd uops in schedulers (5a)dispatch uop (78)map ldst uop (7d)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)
1005134110191101810001688310001000200011000
1004103910011100010001688310001000200011000
1004103910011100010001688310001000200011000
1004103910011100010001688310001000200011000
1004103910011100010001688310001000200011000
1004103910011100010001688310001000200011000
1004103910011100010001688310001000200011000
1004103910011100010001688310001000200011000
1004103910011100010001688310001000200011000
1004103910011100010001690110001000200011000

Test 2: throughput

Count: 8

Code:

  str q0, [x6, #0x10]
  str q0, [x6, #0x10]
  str q0, [x6, #0x10]
  str q0, [x6, #0x10]
  str q0, [x6, #0x10]
  str q0, [x6, #0x10]
  str q0, [x6, #0x10]
  str q0, [x6, #0x10]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
802058042380119101800181008000130013599748010120080008200160016180000100
802048003780101101800001008000130013598508010120080008200160016180000100
802048003780101101800001008000130013598508010120080008200160016180000100
802048003780101101800001008000130013598508010120080008200160016180000100
802048003780101101800001008000130013583268010120080008200160016180000100
802048003980101101800001008000130013598508010120080008200160016180000100
802048004080101101800001008000130013598508010120080008200160016180000100
802048003780101101800001008000130013598508010120080008200160016180000100
802048003780101101800001008000130013599048010120080008200160016180000100
802048003780101101800001008000130013598508010120080008200160016180000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0009

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
800258007380028118001710800033013599688001320800102016000018000010
800248104380191118018010808283013848208083820809432016065618000010
800248004580011118000010800003013600078001020800002016000018000010
800248004580011118000010800003013600078001020800002016000018000010
800248004580011118000010800003013600078001020800002016000018000010
800248004580011118000010800363013610788004620800412016008218000010
800248004580011118000010800003013600078001020800002016000018000010
800248004580011118000010800003013600078001020800002016000018000010
800248004580011118000010800003013600078001020800002016000018000010
800248004580011118000010800003013600078001020800002016000018000010