Icestorm: STUR (D) measurements

Code:

  stur d0, [x6, #1]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	1148	1019	1	1018	1000	0	16847	1000	0	1000	2000	1	1000
1004	1037	1001	1	1000	1000	0	16847	1000	0	1000	2000	1	1000
1004	1037	1001	1	1000	1000	0	16847	1000	0	1000	2000	1	1000
1004	1037	1001	1	1000	1000	0	16847	1000	0	1000	2000	1	1000
1004	1037	1001	1	1000	1000	0	16847	1000	0	1000	2000	1	1000
1004	1037	1001	1	1000	1000	0	16847	1000	0	1000	2000	1	1000
1004	1037	1001	1	1000	1000	0	16847	1000	0	1000	2000	1	1000
1004	1037	1001	1	1000	1000	0	16847	1000	0	1000	2000	1	1000
1004	1037	1001	1	1000	1000	0	16865	1000	0	1000	2000	1	1000
1004	1037	1001	1	1000	1000	0	16847	1000	0	1000	2000	1	1000

Count: 8

Code:

  stur d0, [x6, #1]
  stur d0, [x6, #1]
  stur d0, [x6, #1]
  stur d0, [x6, #1]
  stur d0, [x6, #1]
  stur d0, [x6, #1]
  stur d0, [x6, #1]
  stur d0, [x6, #1]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80205	80153	80119	101	80018	100	80001	300	1359938	80101	200	80008	200	160016	1	80000	100
80204	80045	80101	101	80000	100	80001	300	1360010	80101	200	80008	200	160016	1	80000	100
80204	80045	80101	101	80000	100	80001	300	1360010	80101	200	80008	200	160016	1	80000	100
80204	80045	80101	101	80000	100	80001	300	1360046	80101	200	80008	200	160016	1	80000	100
80204	80045	80101	101	80000	100	80037	300	1360132	80137	200	80052	200	160016	1	80000	100
80204	80045	80101	101	80000	100	80001	300	1360010	80101	200	80008	200	160016	1	80000	100
80204	80045	80101	101	80000	100	80001	300	1360010	80101	200	80008	200	160016	1	80000	100
80204	80045	80101	101	80000	100	80001	300	1360010	80101	200	80008	200	160016	1	80000	100
80204	80045	80101	101	80000	100	80001	300	1360010	80101	200	80008	200	160016	1	80000	100
80204	80045	80101	101	80000	100	80001	300	1360010	80101	200	80008	200	160016	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80025	80165	80029	11	80018	10	80001	30	1359974	80011	20	80008	20	160016	0	1	80000	0	10
80024	80049	80011	11	80000	10	80001	30	1360010	80011	20	80008	20	160016	0	1	80000	0	10
80024	80047	80011	11	80000	10	80001	30	1360046	80011	20	80008	20	160016	0	1	80000	0	10
80024	80047	80011	11	80000	10	80001	30	1360046	80011	20	80008	20	160016	0	1	80000	0	10
80024	80047	80011	11	80000	10	80001	30	1360046	80011	20	80008	20	160016	0	1	80000	0	10
80024	80047	80011	11	80000	10	80001	30	1360046	80011	20	80008	20	160016	0	1	80000	0	10
80024	80047	80011	11	80000	10	80001	30	1360046	80011	20	80008	20	160000	0	1	80000	0	10
80024	80047	80011	11	80000	10	80000	30	1360043	80010	20	80000	20	160082	0	1	80000	0	10
80024	80047	80011	11	80000	10	80000	30	1360043	80010	20	80000	20	160000	0	1	80000	0	10
80024	80047	80011	11	80000	10	80000	30	1360043	80010	20	80000	20	160000	0	1	80000	0	10

STUR (D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations