Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

STUR (Q)

Test 1: uops

Code:

  stur q0, [x6, #1]
  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch ldst uop (58)simd uops in schedulers (5a)dispatch uop (78)map ldst uop (7d)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)
1005115110191101810001700710001000200011000
1004104510011100010001700710001000200011000
1004104510011100010001700710001000200011000
1004104510011100010001700710001000200011000
1004104510011100010001700710001000200011000
1004104510011100010001700710001000200011000
1004104510011100010001700710001000200011000
1004104510011100010001700710001000200011000
1004104510011100010001700710001000200011000
1004104510011100010001700710001000200011000

Test 2: throughput

Count: 8

Code:

  stur q0, [x6, #1]
  stur q0, [x6, #1]
  stur q0, [x6, #1]
  stur q0, [x6, #1]
  stur q0, [x6, #1]
  stur q0, [x6, #1]
  stur q0, [x6, #1]
  stur q0, [x6, #1]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
806838343480605397802083618003730013601328013720080052200160016180000100
802048004580101101800001008000130013600108010120080008200160016180000100
802048004580101101800001008000130013600108010120080008200160016180000100
802048005280101101800001008000130013600648010120080008200160016180000100
802048004780101101800001008000130013600468010120080008200160016180000100
802048004780101101800001008003730013601688013720080052200160016180000100
802048004780101101800001008000130013600468010120080008200160016180000100
802048004780101101800001008000130013600468010120080008200160016180000100
802048004780101101800001008000130013600468010120080008200160016180000100
802048004780101101800001008000130013600468010120080008200160016180000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
800258014580029118001810800003013600078001020800002016000018000010
800248004580011118000010800003013600078001020800002016000018000010
800248004580011118000010800003013600078001020800002016000018000010
800248004580011118000010800003013600078001020800002016000018000010
800248004580011118000010800003013600078001020800002016000018000010
800248004580011118000010800003013600078001020800002016000018000010
800248004580011118000010800373013601328004720800522016000018000010
800248004580011118000010800003013600078001020800002016000018000010
800248004580011118000010800003013601158001020800002016000018000010
800248004580011118000010800003013600078001020800002016000018000010