Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SUBHN2 (vector, 4S)

Test 1: uops

Code:

  subhn2 v0.8h, v1.4s, v2.4s
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000

Test 2: Latency 1->1

Code:

  subhn2 v0.8h, v1.4s, v2.4s
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010

Test 3: Latency 1->2

Code:

  subhn2 v0.8h, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020430033101011011000010010000300768905101002001000620030018110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030132110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
100243003310021211000002010000707689051002020100042030012111000010
100243003310021211000002010000707689051002020100002030000111000010
100243003310021211000002010000707689051002020100002030000111000010
100243003310021211000002010000707689051002020100002030000111000010
100243003310021211000002010000707689051002020100002030000111000010
100243003310021211000002010000707689051002020100002030000111000010
100243003310021211000002010000707689051002020100002030000111000010
100243003310021211000002010000707689051002020100002030000111000010
100243003310021211000002010000707689051002020100002030000111000010
100243003310021211000002010000707689051002020100002030132111000010

Test 4: Latency 1->3

Code:

  subhn2 v0.8h, v1.4s, v0.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020430033101011011000010010000300768905101002001000620030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000620030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024300331002121100002010000707689051002020100042030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  subhn2 v0.8h, v8.4s, v9.4s
  movi v1.16b, 0
  subhn2 v1.8h, v8.4s, v9.4s
  movi v2.16b, 0
  subhn2 v2.8h, v8.4s, v9.4s
  movi v3.16b, 0
  subhn2 v3.8h, v8.4s, v9.4s
  movi v4.16b, 0
  subhn2 v4.8h, v8.4s, v9.4s
  movi v5.16b, 0
  subhn2 v5.8h, v8.4s, v9.4s
  movi v6.16b, 0
  subhn2 v6.8h, v8.4s, v9.4s
  movi v7.16b, 0
  subhn2 v7.8h, v8.4s, v9.4s
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1602044046480110101800091008001330032005680113200800132002400391160000100
1602044011080110101800091008001330032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032020480150200800502002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005680113200800132002400361160000100
1602044008680109101800081008001230032005280112200800122002403631160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5053

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1600254396680056118004510800493032005680023208001320240000116000010
1600244133780011118000010800003032000080010208000020240000116000010
1600244042480011118000010800003032000080010208000020240000116000010
1600244042880011118000010800003032000080010208000020240000116000010
1600244042380011118000010800003032000080010208000020240000116000010
1600244041780011118000010800003032000080010208000020240000116000010
1600244041780011118000010800003032000080010208000020240000116000010
1600244039580011118000010800003032000080010208000020240000116000010
1600244041780011118000010800003032000080010208000020240000116000010
1600244041780011118000010800003032000080010208000020240000116000010

Test 6: throughput

Count: 16

Code:

  subhn2 v0.8h, v16.4s, v17.4s
  subhn2 v1.8h, v16.4s, v17.4s
  subhn2 v2.8h, v16.4s, v17.4s
  subhn2 v3.8h, v16.4s, v17.4s
  subhn2 v4.8h, v16.4s, v17.4s
  subhn2 v5.8h, v16.4s, v17.4s
  subhn2 v6.8h, v16.4s, v17.4s
  subhn2 v7.8h, v16.4s, v17.4s
  subhn2 v8.8h, v16.4s, v17.4s
  subhn2 v9.8h, v16.4s, v17.4s
  subhn2 v10.8h, v16.4s, v17.4s
  subhn2 v11.8h, v16.4s, v17.4s
  subhn2 v12.8h, v16.4s, v17.4s
  subhn2 v13.8h, v16.4s, v17.4s
  subhn2 v14.8h, v16.4s, v17.4s
  subhn2 v15.8h, v16.4s, v17.4s
  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
16020480059160108101160007100160011300640044160110200160014200048004210160000100
16020480035160107101160006100160010300640044160110200160013200048003910160000100
16020480035160107101160006100160010300640036160108200160012200048003910160000100
16020480035160105101160004100160008300640036160108200160012200048003610160000100
16020480035160105101160004100160008300640036160108200160012200048003610160000100
16020480035160105101160004100160008300640036160108200160012200048003610160000100
16020580070160143101160042100160054300640036160108200160012200048003610160000100
16020480035160105101160004100160008300640036160108200160012200048003610160000100
16020480035160105101160004100160008300640036160108200160012200048003610160000100
16020480035160105101160004100160008300640036160108200160012200048003610160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1600248026116001711160006010160010306400441600202016001420480000116000010
1600248010216001111160000010160000306402161600662016006320480000116000010
1600248003516001111160000010160000306400001600102016000020480000116000010
1600248003516001111160000010160000306400001600102016000020480000116000010
1600248003516001111160000010160000306400001600102016000020480000116000010
1600248003516001111160000010160000306400001600102016000020480000116000010
1600248003516001111160000010160000306400001600102016000020480000116000010
168703110173167150455116004325564206160055306400441600202016001320480042116000010
1600248038116001711160006010160010306400001600102016000020480000116000010
1600248003516001111160000010160000306400001600102016000020480000116000010