Icestorm: SUQADD (vector, 16B) measurements

Code:

  suqadd v0.16b, v1.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000

Test 2: Latency 1->1

Code:

  suqadd v0.16b, v1.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10006	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10205	30066	10109	103	10006	102	10031	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0531

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10958	40923	11267	696	10094	477	674	10395	66	775457	10416	20	10478	20	21028	11	10000	10
10024	30649	10119	23	10096	0	22	10396	72	773819	10319	22	10354	20	20632	11	10000	10
10024	30749	10135	23	10112	0	22	10462	76	775427	10420	24	10482	22	21034	12	10000	10
10024	30747	10135	23	10112	0	22	10462	63	774885	10383	20	10430	22	21030	12	10000	10
10024	30779	10133	21	10112	0	20	10462	79	776330	10484	24	10559	20	21100	11	10000	10
10024	30747	10133	21	10112	0	20	10462	69	775401	10418	22	10468	20	20878	11	10000	10
14821	49687	13970	2370	10134	1466	2153	10371	67	774896	10383	20	10437	20	20628	11	10000	10
10024	30646	10117	21	10096	0	20	10396	64	775769	10447	20	10519	20	20874	11	10000	10
10024	30492	10095	23	10072	0	22	10297	74	774365	10352	22	10394	20	20726	11	10000	10
10025	30513	10093	23	10070	0	22	10295	67	771977	10216	20	10241	24	20802	13	10000	10

Test 3: Latency 1->2

Code:

  suqadd v0.16b, v0.16b

Initialization

  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10205	30066	10107	101	10006	100	10031	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	202	20092	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
10024	30033	10021	21	10000	20	10000	0	70	0	768905	10020	20	0	10000	20	0	20000	11	0	10000	10
10024	30033	10021	21	10000	20	10000	0	70	0	768905	10020	20	0	10000	20	0	20000	11	0	10000	10
10024	30033	10021	21	10000	20	10000	0	70	0	768905	10020	20	0	10000	20	0	20000	11	0	10000	10
10024	30033	10021	21	10000	20	10000	0	70	0	768905	10020	20	0	10000	20	0	20000	11	0	10000	10
10024	30033	10021	21	10000	20	10000	0	70	0	768905	10020	20	0	10000	20	0	20000	11	0	10000	10
10024	30033	10021	21	10000	20	10000	0	70	0	768905	10020	20	0	10000	20	0	20000	11	0	10000	10
10024	30033	10021	21	10000	20	10000	0	70	0	768905	10020	20	0	10000	20	0	20000	11	0	10000	10
10024	30033	10021	21	10000	20	10000	0	70	0	768905	10020	20	0	10000	374	321	20096	173	118	10001	227
10024	30033	10021	21	10000	20	10000	0	70	0	768905	10020	20	0	10000	20	0	20000	11	0	10000	10
10024	30033	10021	21	10000	20	10000	0	68	0	769247	10051	20	0	10048	20	0	20000	11	0	10000	10

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  suqadd v0.16b, v8.16b
  movi v1.16b, 0
  suqadd v1.16b, v8.16b
  movi v2.16b, 0
  suqadd v2.16b, v8.16b
  movi v3.16b, 0
  suqadd v3.16b, v8.16b
  movi v4.16b, 0
  suqadd v4.16b, v8.16b
  movi v5.16b, 0
  suqadd v5.16b, v8.16b
  movi v6.16b, 0
  suqadd v6.16b, v8.16b
  movi v7.16b, 0
  suqadd v7.16b, v8.16b

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160204	40485	80110	101	80009	100	80013	300	320052	80112	200	80012	200	160026	1	160000	100
160204	40110	80110	101	80009	100	80013	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	160024	1	160000	100
160205	40132	80145	101	80044	100	80048	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40099	80110	101	80009	100	80013	300	320056	80113	200	80013	200	160024	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5052

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160024	43778	80020	11	80009	10	80013	30	320000	80010	20	80000	20	160000	1	160000	10
160024	41324	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40420	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40390	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40395	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40421	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40388	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40416	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40416	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40398	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10

Test 5: throughput

Count: 16

Code:

  suqadd v0.16b, v16.16b
  suqadd v1.16b, v16.16b
  suqadd v2.16b, v16.16b
  suqadd v3.16b, v16.16b
  suqadd v4.16b, v16.16b
  suqadd v5.16b, v16.16b
  suqadd v6.16b, v16.16b
  suqadd v7.16b, v16.16b
  suqadd v8.16b, v16.16b
  suqadd v9.16b, v16.16b
  suqadd v10.16b, v16.16b
  suqadd v11.16b, v16.16b
  suqadd v12.16b, v16.16b
  suqadd v13.16b, v16.16b
  suqadd v14.16b, v16.16b
  suqadd v15.16b, v16.16b

Initialization

  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160204	80050	160107	101	160006	100	160010	300	640036	160108	200	160012	200	320024	1	160000	100
160204	80035	160107	101	160006	100	160010	300	640044	160110	200	160014	200	320024	1	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	320024	1	160000	100
160204	80035	160105	101	160004	100	160008	300	640044	160110	200	160014	200	320024	1	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	320024	1	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	320024	1	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	320024	1	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	320024	1	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	320024	1	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	320024	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160024	80156	160027	21	160006	20	160010	0	70	0	640000	160020	20	0	160000	20	0	320000	11	0	160000	10
160024	80040	160021	21	160000	20	160000	0	70	0	640000	160020	20	0	160000	20	0	320000	11	0	160000	10
160024	80035	160021	21	160000	20	160000	0	70	0	640000	160020	20	0	160000	20	0	320000	11	0	160000	10
160024	80035	160021	21	160000	20	160000	0	70	0	640000	160020	20	0	160000	20	0	320134	11	0	160000	10
160024	80035	160021	21	160000	20	160000	0	70	0	640000	160020	20	0	160000	20	0	320000	11	0	160000	10
160024	80035	160021	21	160000	20	160000	0	70	0	640000	160020	20	0	160000	20	0	320000	11	0	160000	10
160025	80070	160063	21	160042	20	160054	0	70	0	640000	160020	20	0	160000	20	0	320000	11	0	160000	10
160024	80035	160021	21	160000	20	160000	0	70	0	640000	160020	20	0	160000	20	0	320000	11	0	160000	10
160024	80035	160021	21	160000	20	160000	0	70	0	640000	160020	20	0	160000	20	0	320000	11	0	160000	10
160024	80035	160021	21	160000	20	160000	0	70	0	640000	160020	20	0	160000	20	0	320000	11	0	160000	10

SUQADD (vector, 16B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations