Icestorm: SUQADD (vector, 2D) measurements

Code:

  suqadd v0.2d, v1.2d

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000

Test 2: Latency 1->1

Code:

  suqadd v0.2d, v1.2d

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10006	200	0	20008	1	0	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	0	20008	1	0	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	0	20008	1	0	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	0	20008	1	0	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	0	20008	1	0	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	0	20008	1	0	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	0	20008	1	0	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	5022	3160	17350	2186	1764	8632	3000
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10006	200	0	20008	1	0	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	0	20008	1	0	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10

Test 3: Latency 1->2

Code:

  suqadd v0.2d, v0.2d

Initialization

  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	307	769247	10133	202	10042	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10004	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20402	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30084	10029	21	10008	20	10033	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20082	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30084	10029	21	10008	20	10033	70	769247	10051	20	10044	20	20000	11	10000	10

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  suqadd v0.2d, v8.2d
  movi v1.16b, 0
  suqadd v1.2d, v8.2d
  movi v2.16b, 0
  suqadd v2.2d, v8.2d
  movi v3.16b, 0
  suqadd v3.2d, v8.2d
  movi v4.16b, 0
  suqadd v4.2d, v8.2d
  movi v5.16b, 0
  suqadd v5.2d, v8.2d
  movi v6.16b, 0
  suqadd v6.2d, v8.2d
  movi v7.16b, 0
  suqadd v7.2d, v8.2d

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160204	40526	80109	101	80008	100	80012	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40110	80110	101	80009	100	80013	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40112	80110	101	80009	100	80013	300	320056	80113	200	80013	200	160024	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	160024	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5053

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160024	43879	80019	11	80008	10	80012	30	320052	80022	20	80012	20	160026	1	160000	10
160024	41249	80020	11	80009	10	80013	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40420	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40427	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40417	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40423	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40400	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40400	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160100	1	160000	10
160024	40470	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40438	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10

Test 5: throughput

Count: 16

Code:

  suqadd v0.2d, v16.2d
  suqadd v1.2d, v16.2d
  suqadd v2.2d, v16.2d
  suqadd v3.2d, v16.2d
  suqadd v4.2d, v16.2d
  suqadd v5.2d, v16.2d
  suqadd v6.2d, v16.2d
  suqadd v7.2d, v16.2d
  suqadd v8.2d, v16.2d
  suqadd v9.2d, v16.2d
  suqadd v10.2d, v16.2d
  suqadd v11.2d, v16.2d
  suqadd v12.2d, v16.2d
  suqadd v13.2d, v16.2d
  suqadd v14.2d, v16.2d
  suqadd v15.2d, v16.2d

Initialization

  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160204	80102	160105	101	160004	100	160008	0	300	0	640044	160110	200	0	160014	200	320024	1	160000	100
160204	80054	160105	101	160004	100	160008	0	300	0	640036	160108	200	0	160012	200	320028	1	160000	100
160204	80035	160105	101	160004	100	160008	0	300	0	640036	160108	200	0	160012	200	320024	1	160000	100
160204	80035	160105	101	160004	100	160008	0	300	0	640036	160108	200	0	160012	200	320024	1	160000	100
160204	80035	160105	101	160004	100	160008	0	300	0	640036	160108	200	0	160012	200	320024	1	160000	100
160204	80035	160105	101	160004	100	160008	0	300	0	640036	160108	200	0	160012	200	320024	1	160000	100
160204	80035	160105	101	160004	100	160008	0	300	0	640036	160108	200	0	160012	200	320024	1	160000	100
160204	80035	160105	101	160004	100	160008	0	300	0	640036	160108	200	0	160012	200	320126	1	160000	100
160204	80035	160105	101	160004	100	160008	0	300	0	640036	160108	200	0	160012	200	320024	1	160000	100
160204	80035	160105	101	160004	100	160008	0	300	0	640036	160108	200	0	160012	200	320024	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160024	80125	160017	11	160006	10	160010	30	640036	160018	20	160012	20	320000	1	160000	10
160025	80122	160048	11	160037	10	160045	30	640000	160010	20	160000	20	320000	1	160000	10
160024	80035	160011	11	160000	10	160000	30	640000	160010	20	160000	20	320000	1	160000	10
160025	80071	160055	11	160044	10	160056	30	640000	160010	20	160000	20	320000	1	160000	10
160024	80035	160011	11	160000	10	160000	30	640000	160010	20	160000	20	320000	1	160000	10
160024	80035	160011	11	160000	10	160000	30	640000	160010	20	160000	20	320000	1	160000	10
160024	80041	160011	11	160000	10	160000	30	640000	160010	20	160000	20	320000	1	160000	10
160024	80063	160011	11	160000	10	160000	30	640000	160010	20	160000	20	320126	1	160000	10
160024	80035	160011	11	160000	10	160000	30	640000	160010	20	160000	20	320126	1	160000	10
160024	80035	160011	11	160000	10	160000	30	640000	160010	20	160000	20	320000	1	160000	10

SUQADD (vector, 2D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations