Icestorm: SUQADD (vector, 4H) measurements

Code:

  suqadd v0.4h, v1.4h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000

Test 2: Latency 1->1

Code:

  suqadd v0.4h, v1.4h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	30033	10101	101	10000	100	10000	0	300	0	768905	10100	200	0	10006	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	0	300	0	768905	10100	200	0	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	0	300	0	768905	10100	200	0	10004	200	20008	1	10000	100
10205	30066	10109	103	10006	102	10031	0	300	0	768905	10100	200	0	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	0	300	0	768905	10100	200	0	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	0	300	0	768905	10100	200	0	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	0	300	0	768905	10100	200	0	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	0	300	0	768905	10100	200	0	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	0	300	0	768905	10100	200	0	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	0	300	0	768905	10100	200	0	10004	200	20008	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
10024	30033	10021	21	10000	0	20	10000	70	768905	10020	20	10000	20	0	20000	11	0	10000	10
10024	30033	10021	21	10000	0	20	10000	70	768905	10020	20	10000	1250	886	20092	575	426	10003	673
10024	30083	10029	21	10008	0	20	10033	68	769436	10053	20	10040	20	0	20080	11	0	10000	10
10024	30135	10037	21	10016	0	20	10066	70	769451	10053	20	10038	20	0	20000	11	0	10000	10
10024	30033	10021	21	10000	0	20	10000	70	768905	10020	20	10000	20	0	20000	11	0	10000	10
10024	30083	10029	21	10008	0	20	10033	68	769451	10053	20	10041	20	0	20000	11	0	10000	10
10024	30185	10045	21	10024	0	20	10099	70	768905	10020	20	10000	20	0	20078	11	0	10000	10
10024	30033	10021	21	10000	0	20	10000	70	768905	10020	20	10000	20	0	20000	11	0	10000	10
10024	30084	10029	21	10008	0	20	10033	70	768905	10020	20	10000	20	0	20000	11	0	10000	10
10024	30186	10045	21	10024	0	20	10099	70	768905	10020	20	10000	20	0	20000	11	0	10000	10

Test 3: Latency 1->2

Code:

  suqadd v0.4h, v0.4h

Initialization

  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	769247	10131	200	10044	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10025	30066	10027	21	10006	20	10031	70	768905	10020	20	10004	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  suqadd v0.4h, v8.4h
  movi v1.16b, 0
  suqadd v1.4h, v8.4h
  movi v2.16b, 0
  suqadd v2.4h, v8.4h
  movi v3.16b, 0
  suqadd v3.4h, v8.4h
  movi v4.16b, 0
  suqadd v4.4h, v8.4h
  movi v5.16b, 0
  suqadd v5.4h, v8.4h
  movi v6.16b, 0
  suqadd v6.4h, v8.4h
  movi v7.16b, 0
  suqadd v7.4h, v8.4h

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160204	40495	80110	101	80009	100	80013	300	320192	80147	200	80047	200	160026	1	160000	100
160204	40108	80110	101	80009	100	80013	300	320052	80112	200	80012	200	160026	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	160026	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	160024	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5053

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160024	43790	80020	11	80009	10	80013	30	320000	80010	20	80000	20	160000	1	160000	10
160024	41223	80011	11	80000	10	80000	30	320200	80059	20	80049	20	160000	1	160000	10
160024	40439	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40419	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40390	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40428	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40412	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40405	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40428	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40384	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10

Test 5: throughput

Count: 16

Code:

  suqadd v0.4h, v16.4h
  suqadd v1.4h, v16.4h
  suqadd v2.4h, v16.4h
  suqadd v3.4h, v16.4h
  suqadd v4.4h, v16.4h
  suqadd v5.4h, v16.4h
  suqadd v6.4h, v16.4h
  suqadd v7.4h, v16.4h
  suqadd v8.4h, v16.4h
  suqadd v9.4h, v16.4h
  suqadd v10.4h, v16.4h
  suqadd v11.4h, v16.4h
  suqadd v12.4h, v16.4h
  suqadd v13.4h, v16.4h
  suqadd v14.4h, v16.4h
  suqadd v15.4h, v16.4h

Initialization

  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160204	80067	160107	101	160006	100	160010	300	640036	160108	200	160012	200	320024	1	160000	100
160204	80045	160105	101	160004	100	160008	300	640036	160108	200	160012	200	320024	1	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	320024	1	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	320130	1	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	320028	1	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	320024	1	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	320024	1	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	320024	1	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	320024	1	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	320024	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160024	80203	160017	11	160006	0	10	160010	30	640000	160010	20	160000	20	320000	1	160000	10
160024	80043	160011	11	160000	0	10	160000	30	640000	160010	20	160000	20	320000	1	160000	10
160024	80035	160011	11	160000	0	10	160000	30	640000	160010	20	160000	20	320000	1	160000	10
160024	80035	160011	11	160000	0	10	160000	30	640000	160010	20	160000	20	320000	1	160000	10
160024	80035	160011	11	160000	0	10	160000	30	640000	160010	20	160000	20	320000	1	160000	10
160024	80035	160011	11	160000	0	10	160000	30	640000	160010	20	160000	20	320000	1	160000	10
160024	80035	160011	11	160000	0	10	160000	30	640000	160010	20	160000	20	320000	1	160000	10
160024	80035	160011	11	160000	0	10	160000	30	640000	160010	20	160000	20	320000	1	160000	10
160024	80035	160011	11	160000	0	10	160000	30	640000	160010	20	160000	20	320000	1	160000	10
160024	80035	160011	11	160000	0	10	160000	30	640000	160010	20	160000	20	320000	1	160000	10

SUQADD (vector, 4H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations