Icestorm: SXTL (8H) measurements

Code:

  sxtl v0.8h, v0.8b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	2033	1001	1	1000	1000	50248	1000	1000	1000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	1000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	1000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	1000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	1000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	1000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	1000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	1000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	1000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	1000	1	1000

Test 2: Latency 1->2

Code:

  sxtl v0.8h, v0.8b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	20085	10113	101	10012	100	10036	300	509248	10100	200	10006	200	10049	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	10004	1	10000	100
10204	20084	10113	101	10012	100	10036	300	509248	10100	200	10004	200	10004	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509780	10136	200	10048	200	10004	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	10004	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	10004	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	10004	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10006	200	10006	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	10004	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	10004	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	20495	10129	21	10108	20	10324	80	513504	10312	24	10332	20	10042	11	10000	10
10024	20449	10117	21	10096	20	10288	66	511376	10164	20	10166	22	10291	12	10000	10
10024	20341	10093	21	10072	20	10216	67	512440	10236	20	10249	20	10249	11	10000	10
10024	20341	10093	21	10072	20	10216	65	512440	10236	20	10247	20	10121	11	10000	10
10024	20342	10093	21	10072	20	10216	67	510844	10128	20	10123	20	10291	11	10000	10
10024	20085	10033	21	10012	20	10036	64	514004	10344	20	10372	20	10040	11	10000	10
10024	20444	10117	21	10096	20	10288	70	509248	10020	20	10000	20	10043	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	10000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	10000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	10000	11	10000	10

Test 3: throughput

Count: 8

Code:

  sxtl v0.8h, v8.8b
  sxtl v1.8h, v8.8b
  sxtl v2.8h, v8.8b
  sxtl v3.8h, v8.8b
  sxtl v4.8h, v8.8b
  sxtl v5.8h, v8.8b
  sxtl v6.8h, v8.8b
  sxtl v7.8h, v8.8b

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
80204	40066	80105	101	80004	100	80008	300	320036	80108	200	80012	200	80014	1	80000	100
80204	40044	80105	101	80004	100	80008	300	320036	80108	200	80012	200	80012	1	80000	100
80204	40034	80105	101	80004	100	80008	300	320036	80108	200	80012	200	80012	1	80000	100
80204	40034	80105	101	80004	100	80008	300	320036	80108	200	80012	200	80012	1	80000	100
80204	40034	80105	101	80004	100	80008	300	320036	80108	200	80012	200	80012	1	80000	100
80204	40034	80105	101	80004	100	80008	300	320036	80108	200	80012	200	80012	1	80000	100
80204	40034	80105	101	80004	100	80008	300	320200	80152	200	80060	200	80012	1	80000	100
80204	40034	80105	101	80004	100	80008	300	320036	80108	200	80012	200	80012	1	80000	100
80204	40034	80105	101	80004	100	80008	300	320036	80108	200	80012	200	80012	1	80000	100
80204	40034	80105	101	80004	100	80008	300	320036	80108	200	80012	200	80012	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
80024	40203	80027	21	80006	20	80010	70	320044	80030	20	80016	20	80018	11	80000	10
80024	40035	80029	21	80008	20	80012	70	320000	80020	20	80000	20	80000	11	80000	10
80024	40034	80021	21	80000	20	80000	70	320000	80020	20	80000	20	80000	11	80000	10
80024	40034	80021	21	80000	20	80000	70	320000	80020	20	80000	20	80000	11	80000	10
80024	40034	80021	21	80000	20	80000	70	320000	80020	20	80000	20	80000	11	80000	10
80024	40034	80021	21	80000	20	80000	70	320000	80020	20	80000	20	80000	11	80000	10
80024	40034	80021	21	80000	20	80000	70	320000	80020	20	80000	20	80000	11	80000	10
80024	40034	80021	21	80000	20	80000	70	320000	80020	20	80000	20	80000	11	80000	10
80024	40034	80021	21	80000	20	80000	70	320000	80020	20	80000	20	80018	11	80000	10
80024	40034	80021	21	80000	20	80000	70	320000	80020	20	80000	20	80018	11	80000	10

SXTL (8H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations