Icestorm: TBL (four register table, 16B) measurements

Code:

  tbl v0.16b, { v0.16b, v1.16b, v2.16b, v3.16b }, v4.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 3.000

Issues: 3.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 3.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
3004	4033	3001	1	3000	3000	100179	3000	3000	9000	1	3000
3004	4033	3001	1	3000	3000	100179	3000	3000	9000	1	3000
3004	4033	3001	1	3000	3000	100179	3000	3000	9000	1	3000
3004	4033	3001	1	3000	3000	100179	3000	3000	9000	1	3000
3004	4033	3001	1	3000	3000	100179	3000	3000	9000	1	3000
3004	4033	3001	1	3000	3000	100179	3000	3000	9000	1	3000
3004	4033	3001	1	3000	3000	100179	3000	3000	9000	1	3000
3004	4033	3001	1	3000	3000	100179	3000	3000	9000	1	3000
3004	4033	3001	1	3000	3000	100179	3000	3000	9000	1	3000
3004	4033	3001	1	3000	3000	100179	3000	3000	9000	1	3000

Test 2: Latency 1->2

Code:

  tbl v0.16b, { v0.16b, v1.16b, v2.16b, v3.16b }, v4.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
30204	40033	30201	201	30000	200	30000	700	1009145	30202	200	30010	200	90024	101	30000	100
30204	40033	30201	201	30000	200	30000	700	1009179	30200	200	30008	200	90024	101	30000	100
30204	40033	30201	201	30000	200	30000	700	1009179	30200	200	30008	200	90024	101	30000	100
30204	40033	30201	201	30000	200	30000	700	1009179	30200	200	30008	200	90024	101	30000	100
30204	40033	30201	201	30000	200	30000	700	1009179	30200	200	30008	200	90024	101	30000	100
30204	40033	30201	201	30000	200	30000	700	1009179	30200	200	30008	200	90024	101	30000	100
30204	40033	30201	201	30000	200	30000	700	1009179	30200	200	30008	200	90024	101	30000	100
30204	40033	30201	201	30000	200	30000	700	1009179	30200	200	30008	200	90024	101	30000	100
30204	40033	30201	201	30000	200	30000	700	1009179	30200	200	30008	200	90024	101	30000	100
30204	40033	30201	201	30000	200	30000	700	1009179	30200	200	30008	200	90024	101	30000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
30024	40033	30011	11	30000	10	30000	30	1009170	30011	20	30010	20	90000	1	30000	10
30024	40033	30011	11	30000	10	30000	30	1009179	30010	20	30000	20	90000	1	30000	10
30024	40033	30011	11	30000	10	30000	30	1009422	30059	20	30060	20	90171	2	30000	10
30024	40033	30011	11	30000	10	30000	30	1009179	30010	20	30000	20	90000	1	30000	10
30024	40033	30011	11	30000	10	30000	30	1009179	30010	20	30000	20	90000	1	30000	10
30024	40033	30011	11	30000	10	30000	30	1009179	30010	20	30000	20	90162	1	30000	10
30024	40033	30011	11	30000	10	30000	30	1009179	30010	20	30000	20	90000	1	30000	10
30024	40033	30011	11	30000	10	30000	30	1009179	30010	20	30000	20	90000	1	30000	10
30024	40033	30011	11	30000	10	30000	30	1009179	30010	20	30000	20	90000	1	30000	10
30024	40033	30011	11	30000	10	30000	30	1009179	30010	20	30000	20	90000	1	30000	10

Test 3: Latency 1->3

Code:

  tbl v1.16b, { v0.16b, v1.16b, v2.16b, v3.16b }, v4.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
30204	40033	30201	201	30000	200	30002	700	1009162	30202	200	30010	200	90030	101	30000	100
30204	40033	30201	201	30000	200	30002	700	1009179	30200	200	30008	200	90024	101	30000	100
30204	40033	30201	201	30000	200	30000	700	1009179	30200	200	30008	200	90024	101	30000	100
30204	40033	30201	201	30000	200	30000	700	1009179	30200	200	30008	200	90024	101	30000	100
30204	40033	30201	201	30000	200	30000	700	1009179	30200	200	30008	200	90024	101	30000	100
30204	40033	30201	201	30000	200	30000	700	1009179	30200	200	30008	200	90192	101	30000	100
30204	40033	30201	201	30000	200	30000	700	1009179	30200	200	30008	200	90024	101	30000	100
30204	40033	30201	201	30000	200	30000	700	1009179	30200	200	30008	200	90024	101	30000	100
30204	40033	30201	201	30000	200	30000	700	1009179	30200	200	30008	200	90024	101	30000	100
30204	40033	30201	201	30000	200	30000	700	1009179	30200	200	30008	200	90024	101	30000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
30024	40033	30011	11	30000	10	30000	30	1009170	30011	20	30010	20	90000	1	30000	10
30024	40033	30011	11	30000	10	30000	30	1009179	30010	20	30000	20	90000	1	30000	10
30024	40033	30011	11	30000	10	30000	30	1009179	30010	20	30000	20	90000	1	30000	10
30024	40033	30011	11	30000	10	30000	30	1009433	30061	20	30068	20	90000	1	30000	10
30024	40033	30011	11	30000	10	30000	30	1009179	30010	20	30000	20	90000	1	30000	10
30024	40033	30011	11	30000	10	30000	30	1009179	30010	20	30000	20	90000	1	30000	10
30024	40033	30011	11	30000	10	30000	30	1009179	30010	20	30000	20	90000	1	30000	10
30024	40033	30011	11	30000	10	30000	30	1009179	30010	20	30000	20	90000	1	30000	10
30024	40033	30011	11	30000	10	30000	30	1009179	30010	20	30000	20	90000	1	30000	10
30024	40033	30011	11	30000	10	30000	30	1009179	30010	20	30000	20	90000	1	30000	10

Test 4: Latency 1->4

Code:

  tbl v2.16b, { v0.16b, v1.16b, v2.16b, v3.16b }, v4.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
32697	48194	32339	1409	30096	834	1263	30134	700	1009166	30202	200	30010	200	90030	101	30000	100
30204	40033	30201	201	30000	0	200	30000	700	1009173	30200	200	30008	200	90024	101	30000	100
30204	40033	30201	201	30000	0	200	30000	700	1009173	30200	200	30008	200	90024	101	30000	100
30204	40033	30201	201	30000	0	200	30000	700	1009173	30200	200	30008	200	90024	101	30000	100
30204	40033	30201	201	30000	0	200	30000	700	1009173	30200	200	30008	200	90024	101	30000	100
30204	40033	30201	201	30000	0	200	30000	700	1009173	30200	200	30008	200	90024	101	30000	100
30204	40033	30201	201	30000	0	200	30000	700	1009173	30200	200	30008	200	90024	101	30000	100
30204	40033	30201	201	30000	0	200	30000	700	1009173	30200	200	30008	200	90024	101	30000	100
30204	40033	30201	201	30000	0	200	30000	700	1009173	30200	200	30008	200	90024	101	30000	100
30204	40033	30201	201	30000	0	200	30000	700	1009173	30200	200	30008	200	90024	101	30000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
30024	40033	30011	11	30000	10	30001	30	1009167	30011	20	30010	20	90000	1	30000	10
30024	40033	30011	11	30000	10	30000	30	1009173	30010	20	30000	20	90000	1	30000	10
30024	40033	30011	11	30000	10	30000	30	1009173	30010	20	30000	20	90000	1	30000	10
30024	40033	30011	11	30000	10	30000	30	1009173	30010	20	30000	20	90000	1	30000	10
30024	40033	30011	11	30000	10	30000	30	1009173	30010	20	30000	20	90000	1	30000	10
30024	40033	30011	11	30000	10	30000	30	1009173	30010	20	30000	20	90000	1	30000	10
30024	40033	30011	11	30000	10	30000	30	1009173	30010	20	30000	20	90000	1	30000	10
30024	40033	30011	11	30000	10	30000	30	1009173	30010	20	30000	20	90000	1	30000	10
30024	40033	30011	11	30000	10	30001	30	1009162	30010	20	30000	20	90000	1	30000	10
30024	40033	30011	11	30000	10	30000	30	1009173	30010	20	30000	20	90000	1	30000	10

Test 5: Latency 1->5

Code:

  tbl v3.16b, { v0.16b, v1.16b, v2.16b, v3.16b }, v4.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
30204	40225	30317	201	30116	0	200	30208	700	1009166	30202	200	30010	200	90030	101	30000	100
30204	40033	30201	201	30000	0	200	30000	700	1009173	30200	200	30008	200	90024	101	30000	100
30204	40033	30201	201	30000	0	200	30000	700	1009173	30200	200	30008	200	90024	101	30000	100
30205	40114	30253	200	30053	0	199	30102	700	1009173	30200	200	30008	200	90024	101	30000	100
30204	40033	30201	201	30000	0	200	30000	700	1009173	30200	200	30008	200	90024	101	30000	100
30204	40033	30201	201	30000	0	200	30000	700	1009173	30200	200	30008	200	90024	101	30000	100
30204	40033	30201	201	30000	0	200	30000	700	1009173	30200	200	30008	200	90024	101	30000	100
31324	61533	31616	3548	25980	2088	3643	26006	700	1009173	30200	200	30008	200	90024	101	30000	100
30204	40033	30201	201	30000	0	200	30000	700	1009173	30200	200	30008	200	90024	101	30000	100
30204	40033	30201	201	30000	0	200	30000	700	1009173	30200	200	30008	200	90024	101	30000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
30024	40033	30011	11	30000	10	30001	30	1009410	30061	20	30062	20	90012	1	30000	10
30024	40033	30011	11	30000	10	30000	30	1009173	30010	20	30000	20	90000	1	30000	10
30024	40033	30011	11	30000	10	30000	30	1009173	30010	20	30000	20	90000	1	30000	10
30024	40033	30011	11	30000	10	30000	30	1009173	30010	20	30000	20	90000	1	30000	10
30024	40033	30011	11	30000	10	30000	30	1009173	30010	20	30000	20	90000	1	30000	10
30025	40066	30035	11	30024	10	30051	30	1009173	30010	20	30000	20	90030	1	30000	10
30025	40066	30035	11	30024	10	30051	30	1009173	30010	20	30004	20	90000	1	30000	10
30024	40033	30011	11	30000	10	30000	30	1009173	30010	20	30000	20	90000	1	30000	10
30024	40033	30011	11	30000	10	30000	30	1009173	30010	20	30000	20	90000	1	30000	10
30024	40033	30011	11	30000	10	30000	30	1009173	30010	20	30000	20	90000	1	30000	10

Test 6: Latency 1->6

Code:

  tbl v4.16b, { v0.16b, v1.16b, v2.16b, v3.16b }, v4.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0034

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
30204	40034	30201	201	30000	200	30001	700	1007088	30202	200	30010	200	90024	101	30000	100
30204	40034	30201	201	30000	200	30002	700	1007125	30201	200	30008	200	90024	101	30000	100
30204	40034	30201	201	30000	200	30001	700	1007125	30201	200	30008	200	90156	101	30000	100
30204	40034	30201	201	30000	200	30001	659	1007464	30239	200	30056	200	90024	101	30000	100
30204	40034	30201	201	30000	200	30001	700	1007125	30201	200	30008	200	90024	101	30000	100
30204	40034	30201	201	30000	200	30001	700	1007125	30201	200	30008	200	90024	101	30000	100
30204	40034	30201	201	30000	200	30001	700	1007125	30201	200	30008	200	90024	101	30000	100
30204	40034	30201	201	30000	200	30001	700	1007125	30201	200	30008	200	90024	101	30000	100
30204	40034	30201	201	30000	200	30001	700	1007125	30201	200	30008	200	90024	101	30000	100
30204	40034	30201	201	30000	200	30001	700	1007125	30201	200	30008	200	90024	101	30000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0034

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
30024	40034	30011	11	30000	10	30000	30	1007133	30011	20	30006	20	90000	1	30000	10
30024	40034	30011	11	30000	10	30000	30	1007120	30010	20	30000	20	90000	1	30000	10
30024	40034	30011	11	30000	10	30000	30	1007120	30010	20	30000	20	90000	1	30000	10
30024	40034	30011	11	30000	10	30000	30	1007120	30010	20	30000	20	90000	1	30000	10
30024	40034	30011	11	30000	10	30000	30	1007120	30010	20	30000	20	90000	1	30000	10
30024	40034	30011	11	30000	10	30000	30	1007120	30010	20	30000	20	90000	1	30000	10
30024	40034	30011	11	30000	10	30000	30	1007120	30010	20	30000	20	90000	1	30000	10
30024	40034	30011	11	30000	10	30000	30	1007120	30010	20	30000	20	90000	1	30000	10
30024	40034	30011	11	30000	10	30000	30	1007120	30010	20	30000	20	90000	1	30000	10
30024	40034	30011	11	30000	10	30000	30	1007120	30010	20	30000	20	90000	1	30000	10

Test 7: throughput

Count: 8

Code:

  tbl v0.16b, { v8.16b, v9.16b, v10.16b, v11.16b }, v12.16b
  tbl v1.16b, { v8.16b, v9.16b, v10.16b, v11.16b }, v12.16b
  tbl v2.16b, { v8.16b, v9.16b, v10.16b, v11.16b }, v12.16b
  tbl v3.16b, { v8.16b, v9.16b, v10.16b, v11.16b }, v12.16b
  tbl v4.16b, { v8.16b, v9.16b, v10.16b, v11.16b }, v12.16b
  tbl v5.16b, { v8.16b, v9.16b, v10.16b, v11.16b }, v12.16b
  tbl v6.16b, { v8.16b, v9.16b, v10.16b, v11.16b }, v12.16b
  tbl v7.16b, { v8.16b, v9.16b, v10.16b, v11.16b }, v12.16b

Initialization

  movi v8.16b, 9
  movi v9.16b, 10
  movi v10.16b, 11
  movi v11.16b, 12
  movi v12.16b, 13

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.5005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
240204	120047	240208	201	240007	200	240012	700	1200045	240210	200	240016	200	720054	101	240000	100
240204	120047	240208	201	240007	200	240012	700	1200049	240210	200	240016	200	720204	100	240000	100
240204	120036	240205	201	240004	200	240010	700	1200049	240210	200	240016	200	720048	101	240000	100
240204	120036	240205	201	240004	200	240010	700	1200049	240210	200	240016	200	720048	101	240000	100
240204	120036	240205	201	240004	200	240010	700	1200049	240210	200	240016	200	720048	101	240000	100
240204	120036	240205	201	240004	200	240010	651	1200266	240258	200	240068	200	720048	101	240000	100
240204	120036	240205	201	240004	200	240010	700	1200049	240210	200	240016	200	720048	101	240000	100
240204	120036	240205	201	240004	200	240010	700	1200049	240210	200	240016	200	720048	101	240000	100
240204	120036	240205	201	240004	200	240010	700	1200049	240210	200	240016	200	720048	101	240000	100
240204	120036	240205	201	240004	200	240010	700	1200049	240210	200	240016	200	720204	101	240000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.5005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
240024	120056	240014	11	240003	10	240008	0	30	0	1200037	240018	20	0	240012	20	720000	1	240000	10
240024	120036	240011	11	240000	10	240000	859	37830	12773	1200205	242386	2007	1038	240050	20	720000	1	240000	10
240026	120127	240087	11	240076	10	240102	0	30	0	1200401	240018	20	0	240012	20	720036	1	240000	10
240025	120072	240051	11	240040	10	240056	0	30	0	1199998	240010	20	0	240000	20	720000	1	240000	10
240024	120036	240011	11	240000	10	240000	0	30	0	1200039	240018	20	0	240012	20	720000	1	240000	10
240024	120036	240011	11	240000	10	240000	0	30	0	1199998	240010	20	0	240000	20	720000	1	240000	10
240024	120036	240011	11	240000	10	240000	0	30	0	1199998	240010	20	0	240000	20	720000	1	240000	10
240024	120036	240011	11	240000	10	240000	0	30	0	1199998	240010	20	0	240000	20	720000	1	240000	10
240025	120072	240047	11	240036	10	240046	0	30	0	1199998	240010	20	0	240000	20	720000	1	240000	10
240024	120036	240011	11	240000	10	240000	0	30	0	1199998	240010	20	0	240000	20	720000	1	240000	10

TBL (four register table, 16B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->4

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: Latency 1->5

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: Latency 1->6

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 7: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations