Icestorm: TBL (four register table, 8B) measurements

Code:

  tbl v0.8b, { v0.16b, v1.16b, v2.16b, v3.16b }, v4.8b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 3.000

Issues: 3.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 3.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
3004	4033	3001	1	3000	3000	100179	3000	3000	9000	1	3000
3004	4033	3001	1	3000	3000	100179	3000	3000	9000	1	3000
3004	4033	3001	1	3000	3000	100179	3000	3000	9000	1	3000
3004	4033	3001	1	3000	3000	100179	3000	3000	9000	1	3000
3004	4033	3001	1	3000	3000	100179	3000	3000	9000	1	3000
3004	4033	3001	1	3000	3000	100179	3000	3000	9333	1	3000
3004	4033	3001	1	3000	3000	100179	3000	3000	9000	1	3000
3004	4033	3001	1	3000	3000	100179	3000	3000	9000	1	3000
3004	4033	3001	1	3000	3000	100179	3000	3000	9000	1	3000
3004	4033	3001	1	3000	3000	100179	3000	3000	9000	1	3000

Test 2: Latency 1->2

Code:

  tbl v0.8b, { v0.16b, v1.16b, v2.16b, v3.16b }, v4.8b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
30204	40033	30201	201	30000	200	30000	700	1009148	30202	200	30010	200	90030	101	30000	100
30204	40033	30201	201	30000	200	30000	700	1009179	30200	200	30008	200	90024	101	30000	100
30204	40033	30201	201	30000	200	30000	700	1009179	30200	200	30008	200	90024	101	30000	100
30204	40033	30201	201	30000	200	30000	700	1009179	30200	200	30008	200	90024	101	30000	100
30204	40033	30201	201	30000	200	30000	700	1009179	30200	200	30008	200	90024	101	30000	100
30204	40033	30201	201	30000	200	30000	668	1009427	30249	200	30063	200	90024	101	30000	100
30204	40033	30201	201	30000	200	30000	700	1009179	30200	200	30008	200	90024	101	30000	100
30204	40033	30201	201	30000	200	30000	700	1009179	30200	200	30008	200	90024	101	30000	100
30204	40033	30201	201	30000	200	30000	700	1009179	30200	200	30008	200	90024	101	30000	100
30204	40033	30201	201	30000	200	30000	700	1009179	30200	200	30008	200	90024	101	30000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
30024	40033	30011	11	30000	10	30000	30	1009399	30059	20	30062	20	90000	1	30000	10
30024	40033	30011	11	30000	10	30000	34	1009422	30060	20	30057	20	90000	1	30000	10
30024	40033	30011	11	30000	10	30000	30	1009179	30010	20	30000	20	90000	1	30000	10
30024	40033	30011	11	30000	10	30000	30	1009179	30010	20	30000	20	90000	1	30000	10
30025	40066	30034	11	30023	10	30049	30	1009618	30062	20	30055	20	90000	1	30000	10
30024	40033	30011	11	30000	10	30000	30	1009179	30010	20	30000	20	90000	1	30000	10
30024	40033	30011	11	30000	10	30000	30	1009179	30010	20	30000	20	90000	1	30000	10
30024	40033	30011	11	30000	10	30000	30	1009179	30010	20	30000	20	90000	1	30000	10
30024	40033	30011	11	30000	10	30000	30	1009179	30010	20	30000	20	90000	1	30000	10
30024	40033	30011	11	30000	10	30000	30	1009179	30010	20	30000	20	90000	1	30000	10

Test 3: Latency 1->3

Code:

  tbl v1.8b, { v0.16b, v1.16b, v2.16b, v3.16b }, v4.8b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
30204	40033	30201	201	30000	200	30000	696	1009384	30248	200	30062	200	90030	101	30000	100
30204	40033	30201	201	30000	200	30000	700	1009179	30200	200	30008	200	90024	101	30000	100
30204	40033	30201	201	30000	200	30002	700	1009179	30200	200	30008	200	90030	101	30000	100
30204	40033	30201	201	30000	200	30000	700	1009179	30200	200	30008	200	90030	101	30000	100
30204	40033	30201	201	30000	200	30000	700	1009179	30200	200	30008	200	90024	101	30000	100
30204	40033	30201	201	30000	200	30000	700	1009179	30200	200	30008	200	90024	101	30000	100
30204	40033	30201	201	30000	200	30000	700	1009179	30200	200	30008	200	90024	101	30000	100
30204	40033	30201	201	30000	200	30000	700	1009179	30200	200	30008	200	90024	101	30000	100
30204	40033	30201	201	30000	200	30000	700	1009179	30200	200	30008	200	90024	101	30000	100
30204	40033	30201	201	30000	200	30000	700	1009179	30200	200	30008	200	90024	101	30000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
30024	40033	30011	11	30000	10	30000	30	1009170	30011	20	30010	20	90000	1	30000	10
30024	40033	30011	11	30000	10	30000	30	1009179	30010	20	30000	20	90000	1	30000	10
30024	40033	30011	11	30000	10	30000	30	1009179	30010	20	30000	20	90000	1	30000	10
30024	40033	30011	11	30000	10	30000	30	1009179	30010	20	30000	20	90000	1	30000	10
30024	40033	30011	11	30000	10	30000	30	1009179	30010	20	30000	20	90000	1	30000	10
30024	40033	30011	11	30000	10	30000	30	1009179	30010	20	30000	20	90000	1	30000	10
30024	40033	30011	11	30000	10	30000	30	1009179	30010	20	30000	20	90000	1	30000	10
30024	40033	30011	11	30000	10	30000	30	1009179	30010	20	30000	20	90000	1	30000	10
30024	40033	30011	11	30000	10	30000	30	1009179	30010	20	30000	20	90000	1	30000	10
30024	40033	30011	11	30000	10	30000	30	1009179	30010	20	30000	20	90000	1	30000	10

Test 4: Latency 1->4

Code:

  tbl v2.8b, { v0.16b, v1.16b, v2.16b, v3.16b }, v4.8b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
30204	40033	30201	201	30000	0	200	30002	0	700	0	1009164	30202	200	0	30010	200	90030	101	30000	100
30204	40033	30201	201	30000	0	200	30000	0	650	0	1009421	30250	200	0	30064	200	90024	101	30000	100
30204	40033	30201	201	30000	0	200	30000	0	700	0	1009173	30200	200	0	30008	200	90024	101	30000	100
30204	40033	30201	201	30000	0	200	30000	0	700	0	1009173	30200	200	0	30008	200	90024	101	30000	100
30204	40033	30201	201	30000	0	200	30000	0	700	0	1009173	30200	200	0	30008	200	90024	101	30000	100
30204	40033	30201	201	30000	0	200	30000	0	700	0	1009173	30200	200	0	30008	200	90024	101	30000	100
30204	40033	30201	201	30000	0	200	30000	0	700	0	1009173	30200	200	0	30008	200	90024	101	30000	100
30204	40033	30201	201	30000	0	200	30000	0	700	0	1009173	30200	200	0	30008	200	90024	101	30000	100
30204	40033	30201	201	30000	0	200	30000	0	700	0	1009173	30200	200	0	30008	200	90024	101	30000	100
30204	40033	30201	201	30000	0	200	30000	0	700	0	1009173	30200	200	0	30008	200	90204	101	30000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
30024	40033	30011	11	30000	10	30000	30	1009162	30010	20	30000	20	90000	1	30000	10
30024	40033	30011	11	30000	10	30000	30	1009173	30010	20	30000	20	90000	1	30000	10
30024	40033	30011	11	30000	10	30000	30	1009173	30010	20	30000	20	90000	1	30000	10
30024	40033	30011	11	30000	10	30000	30	1009173	30010	20	30000	20	90000	1	30000	10
30024	40033	30011	11	30000	10	30000	30	1009173	30010	20	30000	20	90000	1	30000	10
30024	40033	30011	11	30000	10	30000	30	1009173	30010	20	30000	20	90000	1	30000	10
30024	40033	30011	11	30000	10	30000	30	1009173	30010	20	30000	20	90000	1	30000	10
30024	40033	30011	11	30000	10	30000	30	1009173	30010	20	30000	20	90000	1	30000	10
30024	40033	30011	11	30000	10	30000	30	1009173	30010	20	30000	20	90000	1	30000	10
30024	40033	30011	11	30000	10	30000	30	1009173	30010	20	30000	20	90000	1	30000	10

Test 5: Latency 1->5

Code:

  tbl v3.8b, { v0.16b, v1.16b, v2.16b, v3.16b }, v4.8b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
30204	40033	30201	201	30000	200	30000	700	1009153	30202	200	30010	200	90030	101	30000	100
30204	40033	30201	201	30000	200	30000	700	1009173	30200	200	30008	200	90024	101	30000	100
30204	40033	30201	201	30000	200	30000	700	1009173	30200	200	30008	200	90024	101	30000	100
30204	40033	30201	201	30000	200	30000	700	1009173	30200	200	30008	200	90024	101	30000	100
30204	40033	30201	201	30000	200	30000	700	1009173	30200	200	30008	200	90024	101	30000	100
30204	40033	30201	201	30000	200	30000	700	1009173	30200	200	30008	200	90024	101	30000	100
30204	40033	30201	201	30000	200	30000	700	1009173	30200	200	30008	200	90024	101	30000	100
30204	40033	30201	201	30000	200	30000	700	1009173	30200	200	30008	200	90024	101	30000	100
30204	40033	30201	201	30000	200	30000	700	1009173	30200	200	30008	200	90024	101	30000	100
30204	40033	30201	201	30000	200	30000	700	1009173	30200	200	30008	200	90024	101	30000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
30024	40033	30011	11	30000	0	10	30000	30	1009173	30010	20	30000	20	90000	1	30000	10
30024	40033	30011	11	30000	0	10	30000	30	1009173	30010	20	30000	20	90000	1	30000	10
30024	40033	30011	11	30000	0	10	30000	30	1009173	30010	20	30000	20	90000	1	30000	10
30024	40033	30011	11	30000	0	10	30000	30	1009173	30010	20	30000	20	90192	1	30000	10
30024	40033	30011	11	30000	0	10	30000	30	1009173	30010	20	30000	20	90000	1	30000	10
30024	40033	30011	11	30000	0	10	30000	30	1009173	30010	20	30000	20	90000	1	30000	10
30024	40033	30011	11	30000	0	10	30000	30	1009173	30010	20	30000	20	90000	1	30000	10
30024	40033	30011	11	30000	0	10	30000	30	1009173	30010	20	30000	20	90000	1	30000	10
30024	40033	30011	11	30000	0	10	30000	30	1009173	30010	20	30000	20	90000	1	30000	10
30024	40033	30011	11	30000	0	10	30000	30	1009173	30010	20	30000	20	90000	1	30000	10

Test 6: Latency 1->6

Code:

  tbl v4.8b, { v0.16b, v1.16b, v2.16b, v3.16b }, v4.8b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0034

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
30204	40034	30201	201	30000	200	30001	700	1007088	30202	200	30010	200	90030	101	30000	100
30204	40034	30201	201	30000	200	30002	700	1007125	30201	200	30008	200	90024	101	30000	100
30204	40034	30201	201	30000	200	30001	700	1007125	30201	200	30008	200	90024	101	30000	100
30204	40034	30201	201	30000	200	30001	700	1007125	30201	200	30008	200	90024	101	30000	100
30204	40034	30201	201	30000	200	30001	700	1007125	30201	200	30008	200	90024	101	30000	100
30204	40034	30201	201	30000	200	30001	700	1007125	30201	200	30008	200	90024	101	30000	100
30204	40034	30201	201	30000	200	30001	700	1007125	30201	200	30008	200	90024	101	30000	100
30204	40034	30201	201	30000	200	30001	700	1007125	30201	200	30008	200	90024	101	30000	100
30204	40034	30201	201	30000	200	30001	700	1007125	30201	200	30008	200	90024	101	30000	100
30204	40034	30201	201	30000	200	30001	700	1007125	30201	200	30008	200	90024	101	30000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0034

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
30024	40034	30011	11	30000	10	30000	30	1007103	30010	20	30000	20	90000	1	30000	10
30024	40034	30011	11	30000	10	30000	30	1007120	30010	20	30000	20	90000	1	30000	10
30024	40034	30011	11	30000	10	30000	30	1007120	30010	20	30000	20	90000	1	30000	10
30024	40034	30011	11	30000	10	30000	30	1007120	30010	20	30000	20	90000	1	30000	10
30024	40034	30011	11	30000	10	30000	30	1007120	30010	20	30000	20	90000	1	30000	10
30024	40034	30011	11	30000	10	30000	30	1007120	30010	20	30000	20	90000	1	30000	10
30024	40034	30011	11	30000	10	30000	30	1007120	30010	20	30000	20	90000	1	30000	10
30024	40034	30011	11	30000	10	30000	30	1007120	30010	20	30000	20	90000	1	30000	10
30024	40034	30011	11	30000	10	30000	30	1007453	30048	20	30055	20	90000	1	30000	10
30024	40034	30011	11	30000	10	30000	30	1007120	30010	20	30000	20	90000	1	30000	10

Test 7: throughput

Count: 8

Code:

  tbl v0.8b, { v8.16b, v9.16b, v10.16b, v11.16b }, v12.8b
  tbl v1.8b, { v8.16b, v9.16b, v10.16b, v11.16b }, v12.8b
  tbl v2.8b, { v8.16b, v9.16b, v10.16b, v11.16b }, v12.8b
  tbl v3.8b, { v8.16b, v9.16b, v10.16b, v11.16b }, v12.8b
  tbl v4.8b, { v8.16b, v9.16b, v10.16b, v11.16b }, v12.8b
  tbl v5.8b, { v8.16b, v9.16b, v10.16b, v11.16b }, v12.8b
  tbl v6.8b, { v8.16b, v9.16b, v10.16b, v11.16b }, v12.8b
  tbl v7.8b, { v8.16b, v9.16b, v10.16b, v11.16b }, v12.8b

Initialization

  movi v8.16b, 9
  movi v9.16b, 10
  movi v10.16b, 11
  movi v11.16b, 12
  movi v12.16b, 13

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.5005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
240204	120058	240205	201	240004	0	200	240010	0	700	0	1200055	240212	200	0	240018	200	720054	101	240000	100
240204	120036	240205	201	240004	0	200	240010	0	700	0	1200049	240210	200	0	240016	200	720048	101	240000	100
240204	120036	240205	201	240004	0	200	240010	0	700	0	1200049	240210	200	0	240016	200	720048	101	240000	100
240204	120036	240205	201	240004	0	200	240010	0	700	0	1200049	240210	200	0	240016	200	720048	101	240000	100
240204	120036	240205	201	240004	0	200	240010	0	700	0	1200049	240210	200	0	240016	200	720048	101	240000	100
240204	120036	240205	201	240004	0	200	240010	0	700	0	1200049	240210	200	0	240016	200	720048	101	240000	100
240204	120036	240205	201	240004	0	200	240010	0	700	0	1200049	240210	200	0	240016	200	720048	101	240000	100
240204	120036	240205	201	240004	0	200	240010	0	700	0	1200049	240210	200	0	240016	200	720048	101	240000	100
240204	120036	240205	201	240004	0	200	240010	0	700	0	1200049	240210	200	0	240016	200	720048	101	240000	100
240204	120036	240205	201	240004	0	200	240010	0	700	0	1200049	240210	200	0	240016	200	720048	101	240000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.5005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
240024	120056	240014	11	240003	10	240008	30	1199996	240010	20	240000	20	720000	1	240000	10
240025	120073	240054	11	240043	10	240058	30	1199996	240010	20	240000	20	720000	1	240000	10
240024	120036	240011	11	240000	10	240000	30	1199998	240010	20	240000	20	720000	1	240000	10
240024	120036	240011	11	240000	10	240000	30	1199998	240010	20	240000	20	720000	1	240000	10
240024	120036	240011	11	240000	10	240000	30	1199998	240010	20	240000	20	720000	1	240000	10
240025	120072	240050	11	240039	10	240054	30	1199998	240010	20	240000	20	720000	1	240000	10
240024	120036	240011	11	240000	10	240000	30	1200266	240068	20	240068	20	720000	1	240000	10
240024	120036	240011	11	240000	10	240000	30	1199998	240010	20	240000	20	720000	1	240000	10
240024	120036	240011	11	240000	10	240000	30	1200039	240018	20	240012	20	720000	1	240000	10
240024	120036	240011	11	240000	10	240000	30	1199998	240010	20	240000	20	720000	1	240000	10

TBL (four register table, 8B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->4

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: Latency 1->5

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: Latency 1->6

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 7: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations