Icestorm: TBL (three register table, 16B) measurements

Code:

  tbl v0.16b, { v0.16b, v1.16b, v2.16b }, v3.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
2004	4033	2001	1	2000	2000	101248	2000	2000	6000	1	2000
2004	4033	2001	1	2000	2000	101248	2000	2000	6000	1	2000
2004	4033	2001	1	2000	2000	101248	2000	2000	6000	1	2000
2004	4033	2001	1	2000	2000	101248	2000	2000	6000	1	2000
2004	4033	2001	1	2000	2000	101248	2000	2000	6000	1	2000
2004	4033	2001	1	2000	2000	101248	2000	2000	6000	1	2000
2004	4033	2001	1	2000	2000	101248	2000	2000	6000	1	2000
2004	4033	2001	1	2000	2000	101248	2000	2000	6000	1	2000
2004	4033	2001	1	2000	2000	101248	2000	2000	6000	1	2000
2004	4033	2001	1	2000	2000	101248	2000	2000	6000	1	2000

Test 2: Latency 1->2

Code:

  tbl v0.16b, { v0.16b, v1.16b, v2.16b }, v3.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
20204	40033	20101	101	20000	100	20000	300	1019248	20100	200	20006	200	60018	1	20000	100
20204	40033	20101	101	20000	100	20000	300	1019248	20100	200	20004	200	60012	1	20000	100
20204	40033	20101	101	20000	100	20000	300	1019248	20100	200	20004	200	60012	1	20000	100
20204	40033	20101	101	20000	100	20000	300	1019248	20100	200	20004	200	60012	1	20000	100
20204	40033	20101	101	20000	100	20000	300	1019248	20100	200	20004	200	60012	1	20000	100
20204	40033	20101	101	20000	100	20000	300	1019248	20100	200	20004	200	60012	1	20000	100
20204	40033	20101	101	20000	100	20000	300	1019248	20100	200	20004	200	60012	1	20000	100
20204	40033	20101	101	20000	100	20000	300	1019248	20100	200	20004	200	60012	1	20000	100
20204	40033	20101	101	20000	100	20000	300	1019248	20100	200	20004	200	60012	1	20000	100
20204	40033	20101	101	20000	100	20000	300	1019248	20100	200	20004	200	60012	1	20000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
20024	40033	20011	11	20000	10	20000	30	1019248	20010	20	20006	20	60000	1	20000	10
20024	40033	20011	11	20000	10	20000	30	1019248	20010	20	20000	20	60000	1	20000	10
20024	40033	20011	11	20000	10	20000	30	1019248	20010	20	20000	20	60000	1	20000	10
20024	40033	20011	11	20000	10	20000	30	1019248	20010	20	20000	20	60000	1	20000	10
20024	40033	20011	11	20000	10	20000	30	1019248	20010	20	20000	20	60000	1	20000	10
20024	40033	20011	11	20000	10	20000	30	1019248	20010	20	20000	20	60000	1	20000	10
20024	40033	20011	11	20000	10	20000	30	1019248	20010	20	20000	20	60000	1	20000	10
20024	40033	20011	11	20000	10	20000	30	1019248	20010	20	20000	20	60000	1	20000	10
20024	40033	20011	11	20000	10	20000	30	1019248	20010	20	20000	20	60000	1	20000	10
20024	40033	20011	11	20000	10	20000	30	1019248	20010	20	20000	20	60000	1	20000	10

Test 3: Latency 1->3

Code:

  tbl v1.16b, { v0.16b, v1.16b, v2.16b }, v3.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
20204	40033	20101	101	20000	0	100	20000	300	1019248	20100	200	20006	200	60012	1	20000	100
20204	40033	20101	101	20000	0	100	20000	300	1019580	20134	200	20048	200	60018	1	20000	100
20204	40033	20101	101	20000	0	100	20000	300	1019248	20100	200	20004	200	60144	2	20000	100
20204	40033	20101	101	20000	0	100	20000	300	1019248	20100	200	20004	200	60012	1	20000	100
20204	40033	20101	101	20000	0	100	20000	300	1019248	20100	200	20004	200	60012	1	20000	100
20204	40033	20101	101	20000	0	100	20000	300	1019248	20100	200	20004	200	60144	2	20000	100
20204	40033	20101	101	20000	0	100	20000	300	1019248	20100	200	20004	200	60012	1	20000	100
20204	40033	20101	101	20000	0	100	20000	300	1019248	20100	200	20004	200	60012	1	20000	100
20204	40033	20101	101	20000	0	100	20000	300	1019248	20100	200	20006	200	60012	1	20000	100
20204	40033	20101	101	20000	0	100	20000	300	1019248	20100	200	20004	200	60012	1	20000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
20024	40033	20011	11	20000	10	20000	30	1019248	20010	20	20000	20	60000	1	20000	10
20024	40033	20011	11	20000	10	20000	30	1019248	20010	20	20000	20	60000	1	20000	10
20024	40033	20011	11	20000	10	20000	30	1019248	20010	20	20000	20	60000	1	20000	10
20024	40033	20011	11	20000	10	20000	30	1019248	20010	20	20000	20	60000	1	20000	10
20024	40033	20011	11	20000	10	20000	30	1019248	20010	20	20000	20	60000	1	20000	10
20024	40033	20011	11	20000	10	20000	30	1019248	20010	20	20000	20	60000	1	20000	10
20024	40033	20011	11	20000	10	20000	30	1019248	20010	20	20000	20	60000	1	20000	10
20024	40033	20011	11	20000	10	20000	30	1020312	20082	20	20080	20	60000	1	20000	10
20024	40033	20011	11	20000	10	20000	30	1019248	20010	20	20000	20	60000	1	20000	10
20024	40033	20011	11	20000	10	20000	30	1019248	20010	20	20000	20	60000	1	20000	10

Test 4: Latency 1->4

Code:

  tbl v2.16b, { v0.16b, v1.16b, v2.16b }, v3.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0035

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
20204	20035	20101	101	20000	100	20001	300	499059	20103	200	20010	200	60024	1	20000	100
20204	20035	20102	101	20001	100	20003	300	499115	20101	200	20008	200	60024	1	20000	100
20204	20035	20101	101	20000	100	20001	300	499115	20101	200	20008	200	60024	1	20000	100
20204	20035	20101	101	20000	100	20001	300	499115	20101	200	20008	200	60024	1	20000	100
20204	20035	20101	101	20000	100	20001	300	499115	20101	200	20008	200	60024	1	20000	100
20204	20035	20101	101	20000	100	20001	300	499115	20101	200	20008	200	60024	1	20000	100
20204	20035	20101	101	20000	100	20001	300	499115	20101	200	20008	200	60024	1	20000	100
20204	20035	20101	101	20000	100	20001	300	499460	20168	200	20076	200	60024	1	20000	100
20204	20035	20101	101	20000	100	20001	300	499469	20170	200	20080	200	60240	1	20000	100
20204	20141	20193	102	20091	101	20139	300	501185	20503	200	20424	202	60438	3	20000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0035

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
20024	20035	20011	11	20000	10	20001	30	499076	20013	20	20010	20	60000	1	20000	10
20024	20035	20011	11	20000	10	20000	30	499110	20010	20	20000	20	60000	1	20000	10
20024	20035	20011	11	20000	10	20000	30	499110	20010	20	20000	20	60000	1	20000	10
20024	20035	20011	11	20000	10	20000	30	499110	20010	20	20000	20	60000	1	20000	10
20024	20035	20011	11	20000	10	20000	30	499110	20010	20	20000	20	60000	1	20000	10
20024	20035	20011	11	20000	10	20000	30	499110	20010	20	20000	20	60000	1	20000	10
20024	20035	20011	11	20000	10	20000	30	499110	20010	20	20000	20	60000	1	20000	10
20024	20035	20011	11	20000	10	20000	30	499115	20011	20	20008	20	60000	1	20000	10
20024	20035	20011	11	20000	10	20000	30	499110	20010	20	20000	20	60000	1	20000	10
20024	20035	20011	11	20000	10	20000	30	499110	20010	20	20000	20	60000	1	20000	10

Test 5: Latency 1->5

Code:

  tbl v3.16b, { v0.16b, v1.16b, v2.16b }, v3.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
20204	40033	20101	101	20000	100	20000	300	1019248	20100	200	20006	200	0	60012	1	0	20000	100
20204	40033	20101	101	20000	100	20000	300	1019248	20100	200	20004	200	0	60012	1	0	20000	100
20204	40033	20101	101	20000	100	20000	300	1019248	20100	200	20004	200	0	60012	1	0	20000	100
20204	40033	20101	101	20000	100	20000	300	1019248	20100	200	20004	200	0	60012	1	0	20000	100
20204	40033	20101	101	20000	100	20000	300	1019248	20100	200	20004	200	0	60012	1	0	20000	100
20204	40033	20101	101	20000	100	20000	300	1019248	20100	200	20004	200	0	60018	1	0	20000	100
20204	40033	20101	101	20000	100	20000	300	1019248	20100	200	20004	200	0	60012	1	0	20000	100
20204	40033	20101	101	20000	100	20000	300	1019248	20100	200	20006	200	0	60012	1	0	20000	100
20204	40033	20101	101	20000	100	20000	300	1019248	20100	200	20004	200	0	60012	1	0	20000	100
20204	40033	20101	101	20000	100	20000	300	1019248	20100	200	20004	200	0	60012	1	0	20000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
20024	40033	20011	11	20000	10	20000	30	1019248	20010	20	20006	20	60000	1	20000	10
20024	40033	20011	11	20000	10	20000	30	1019248	20010	20	20000	20	60000	1	20000	10
20024	40033	20011	11	20000	10	20000	30	1019248	20010	20	20000	20	60000	1	20000	10
20024	40033	20011	11	20000	10	20000	30	1019248	20010	20	20000	20	60000	1	20000	10
20024	40033	20011	11	20000	10	20000	30	1019248	20010	20	20000	20	60000	1	20000	10
20024	40033	20011	11	20000	10	20000	30	1019248	20010	20	20000	20	60000	1	20000	10
20024	40033	20011	11	20000	10	20000	30	1019248	20010	20	20000	20	60000	1	20000	10
20024	40033	20011	11	20000	10	20000	30	1019248	20010	20	20000	20	60000	1	20000	10
20024	40033	20011	11	20000	10	20000	30	1019248	20010	20	20000	20	60000	1	20000	10
20024	40033	20011	11	20000	10	20000	30	1019248	20010	20	20000	20	60000	1	20000	10

Test 6: throughput

Count: 8

Code:

  tbl v0.16b, { v8.16b, v9.16b, v10.16b }, v11.16b
  tbl v1.16b, { v8.16b, v9.16b, v10.16b }, v11.16b
  tbl v2.16b, { v8.16b, v9.16b, v10.16b }, v11.16b
  tbl v3.16b, { v8.16b, v9.16b, v10.16b }, v11.16b
  tbl v4.16b, { v8.16b, v9.16b, v10.16b }, v11.16b
  tbl v5.16b, { v8.16b, v9.16b, v10.16b }, v11.16b
  tbl v6.16b, { v8.16b, v9.16b, v10.16b }, v11.16b
  tbl v7.16b, { v8.16b, v9.16b, v10.16b }, v11.16b

Initialization

  movi v8.16b, 9
  movi v9.16b, 10
  movi v10.16b, 11
  movi v11.16b, 12

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160204	80056	160103	101	160002	100	160008	300	800051	160110	200	160014	200	480036	1	160000	100
160204	80036	160103	101	160002	100	160008	300	800041	160108	200	160012	200	480036	1	160000	100
160204	80036	160103	101	160002	100	160008	300	800250	160154	200	160064	200	480036	1	160000	100
160204	80036	160103	101	160002	100	160008	300	800041	160108	200	160012	200	480036	1	160000	100
160204	80036	160103	101	160002	100	160008	300	800041	160108	200	160012	200	480036	1	160000	100
160205	80072	160141	101	160040	100	160056	300	800041	160108	200	160012	200	480036	1	160000	100
160204	80036	160103	101	160002	100	160008	300	800250	160154	200	160064	200	480192	1	160000	100
160204	80046	160105	101	160004	100	160010	300	800041	160108	200	160012	200	480036	1	160000	100
160204	80036	160103	101	160002	100	160008	300	800041	160108	200	160012	200	480036	1	160000	100
160204	80036	160103	101	160002	100	160008	300	800041	160108	200	160012	200	480036	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160024	80036	160015	11	160004	10	160010	30	800000	160010	20	160000	20	480000	1	160000	10
160024	80036	160011	11	160000	10	160000	30	800000	160010	20	160000	20	480000	1	160000	10
160024	80036	160011	11	160000	10	160000	30	800000	160010	20	160000	20	480000	1	160000	10
160024	80036	160011	11	160000	10	160000	30	800000	160010	20	160000	20	480000	1	160000	10
160024	80036	160011	11	160000	10	160000	30	800000	160010	20	160000	20	480000	1	160000	10
160024	80036	160011	11	160000	10	160000	30	800000	160010	20	160000	20	480000	1	160000	10
160024	80036	160011	11	160000	10	160000	30	800250	160064	20	160064	20	480000	1	160000	10
160024	80036	160011	11	160000	10	160000	30	800000	160010	20	160000	20	480000	1	160000	10
160024	80036	160011	11	160000	10	160000	30	800000	160010	20	160000	20	480000	1	160000	10
160024	80036	160011	11	160000	10	160000	30	800000	160010	20	160000	20	480000	1	160000	10

TBL (three register table, 16B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->4

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: Latency 1->5

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations