Icestorm: TBL (two register table, 16B) measurements

Code:

  tbl v0.16b, { v0.16b, v1.16b }, v2.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	2033	1001	1	1000	1000	50248	1000	1000	3000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	3000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	3000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	3000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	3000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	3000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	3000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	3000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	3000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	3000	1	1000

Test 2: Latency 1->2

Code:

  tbl v0.16b, { v0.16b, v1.16b }, v2.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10004	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10

Test 3: Latency 1->3

Code:

  tbl v1.16b, { v0.16b, v1.16b }, v2.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10025	20066	10029	21	10008	20	10034	0	70	0	509248	10020	20	0	10004	20	30012	11	10000	10
10024	20033	10021	21	10000	20	10000	0	70	0	509248	10020	20	0	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	0	70	0	509248	10020	20	0	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	0	70	0	509248	10020	20	0	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	0	70	0	509248	10020	20	0	10004	20	30135	11	10000	10
10024	20033	10021	21	10000	20	10000	0	70	0	509248	10020	20	0	10004	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	0	70	0	509248	10020	20	0	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	0	70	0	509248	10020	20	0	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	0	70	0	509248	10020	20	0	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	3481	83073	40121	53436	10508	8118	4011	1102	20	30000	11	10000	10

Test 4: Latency 1->4

Code:

  tbl v2.16b, { v0.16b, v1.16b }, v2.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30012	1	10000	100
10204	20228	10113	101	10012	100	10036	300	509248	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30012	1	10000	100
10205	20066	10111	103	10008	102	10034	300	509248	10100	200	10004	200	30012	1	10000	100
10205	20066	10109	101	10008	100	10034	300	509248	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	202	30141	2	10000	100
10204	20137	10125	101	10024	100	10072	300	509248	10100	200	10004	200	30012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	30000	11	10000	10

Test 5: throughput

Count: 8

Code:

  tbl v0.16b, { v8.16b, v9.16b }, v10.16b
  tbl v1.16b, { v8.16b, v9.16b }, v10.16b
  tbl v2.16b, { v8.16b, v9.16b }, v10.16b
  tbl v3.16b, { v8.16b, v9.16b }, v10.16b
  tbl v4.16b, { v8.16b, v9.16b }, v10.16b
  tbl v5.16b, { v8.16b, v9.16b }, v10.16b
  tbl v6.16b, { v8.16b, v9.16b }, v10.16b
  tbl v7.16b, { v8.16b, v9.16b }, v10.16b

Initialization

  movi v8.16b, 9
  movi v9.16b, 10
  movi v10.16b, 11

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
80204	40045	80107	101	80006	100	80010	300	320036	80108	200	80012	200	240036	1	80000	100
80204	40043	80105	101	80004	100	80008	300	320036	80108	200	80012	200	240036	1	80000	100
80204	40034	80105	101	80004	100	80008	300	320036	80108	200	80012	200	240036	1	80000	100
80204	40034	80105	101	80004	100	80008	300	320036	80108	200	80012	200	240036	1	80000	100
80204	40034	80105	101	80004	100	80008	300	320036	80108	200	80012	200	240036	1	80000	100
80204	40034	80105	101	80004	100	80008	300	320036	80108	200	80012	200	240036	1	80000	100
80204	40034	80105	101	80004	100	80008	300	320036	80108	200	80012	200	240036	1	80000	100
80204	40034	80105	101	80004	100	80008	300	320036	80108	200	80012	200	240036	1	80000	100
80204	40034	80105	101	80004	100	80008	300	320036	80108	200	80012	200	240036	1	80000	100
80204	40034	80105	101	80004	100	80008	300	320036	80108	200	80012	200	240036	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80024	40156	80027	21	80006	20	80010	70	320000	80020	20	80000	20	0	240000	11	0	80000	10
80024	40034	80021	21	80000	20	80000	70	320000	80020	20	80000	20	0	240000	11	0	80000	10
80024	40034	80021	21	80000	20	80000	70	320000	80020	20	80000	20	0	240000	11	0	80000	10
80025	40070	80065	21	80044	20	80056	70	320052	80032	20	80018	20	0	240000	11	0	80000	10
80024	40034	80021	21	80000	20	80000	70	320000	80020	20	80000	20	0	240000	11	0	80000	10
80024	40034	80021	21	80000	20	80000	70	320000	80020	20	80000	20	0	240000	11	0	80000	10
80024	40034	80021	21	80000	20	80000	70	320000	80020	20	80000	20	0	240000	11	0	80000	10
80024	40034	80021	21	80000	20	80000	70	320000	80020	20	80000	20	0	240000	11	0	80000	10
80024	40034	80021	21	80000	20	80000	70	320000	80020	20	80000	20	0	240000	11	0	80000	10
80024	40034	80021	21	80000	20	80000	70	320000	80020	20	80000	20	0	240000	11	0	80000	10

TBL (two register table, 16B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->4

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations