Icestorm: TBX (four register table, 16B) measurements

Code:

  tbx v0.16b, { v1.16b, v2.16b, v3.16b, v4.16b }, v5.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4
  movi v4.16b, 5
  movi v5.16b, 6

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 4.000

Issues: 4.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 4.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
4004	8033	4001	1	4000	4000	203248	4000	4000	12000	1	4000
4004	8033	4001	1	4000	4000	203248	4000	4000	12000	1	4000
4004	8033	4001	1	4000	4000	203248	4000	4000	12000	1	4000
4004	8033	4001	1	4000	4000	203248	4000	4000	12000	1	4000
4004	8033	4001	1	4000	4000	203248	4000	4000	12000	1	4000
4004	8033	4001	1	4000	4000	203248	4000	4000	12000	1	4000
4004	8033	4001	1	4000	4000	203248	4000	4000	12000	1	4000
4004	8033	4001	1	4000	4000	203248	4000	4000	12000	1	4000
4004	8033	4001	1	4000	4000	203248	4000	4000	12000	1	4000
4004	8033	4001	1	4000	4000	203248	4000	4000	12000	1	4000

Test 2: Latency 1->1

Code:

  tbx v0.16b, { v1.16b, v2.16b, v3.16b, v4.16b }, v5.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4
  movi v4.16b, 5
  movi v5.16b, 6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 8.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
40204	80033	40101	101	40000	100	40000	300	2039248	40100	200	40008	200	120024	1	40000	100
40204	80033	40101	101	40000	100	40000	300	2039248	40100	200	40008	200	120024	1	40000	100
40204	80033	40101	101	40000	100	40000	300	2039248	40100	200	40008	200	120024	1	40000	100
40204	80033	40101	101	40000	100	40000	300	2039248	40100	200	40008	200	120024	1	40000	100
40204	80033	40101	101	40000	100	40000	300	2039248	40100	200	40008	200	120024	1	40000	100
40204	80033	40101	101	40000	100	40000	300	2039248	40100	200	40008	200	120024	1	40000	100
40204	80033	40101	101	40000	100	40000	300	2039248	40100	200	40008	200	120024	1	40000	100
40204	80033	40101	101	40000	100	40000	300	2039248	40100	200	40008	200	120024	1	40000	100
40204	80033	40101	101	40000	100	40000	300	2039248	40100	200	40008	200	120024	1	40000	100
40204	80033	40101	101	40000	100	40000	300	2039248	40100	200	40008	200	120024	1	40000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 8.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
40024	80033	40011	11	40000	10	40000	30	2039248	40010	20	40000	20	120000	1	40000	10
40024	80033	40011	11	40000	10	40000	30	2039248	40010	20	40000	20	120000	1	40000	10
40024	80033	40011	11	40000	10	40000	30	2039248	40010	20	40000	20	120000	1	40000	10
40024	80033	40011	11	40000	10	40000	30	2039248	40010	20	40000	20	120000	1	40000	10
40025	80066	40019	11	40008	10	40034	30	2039248	40010	20	40000	20	120000	1	40000	10
40024	80033	40011	11	40000	10	40000	30	2039248	40010	20	40000	20	120000	1	40000	10
40024	80033	40011	11	40000	10	40000	30	2039248	40010	20	40000	20	120000	1	40000	10
40024	80033	40011	11	40000	10	40000	30	2039248	40010	20	40000	20	120000	1	40000	10
40024	80033	40011	11	40000	10	40000	30	2039248	40010	20	40000	20	120000	1	40000	10
40024	80033	40011	11	40000	10	40000	30	2039248	40010	20	40000	20	120000	1	40000	10

Test 3: Latency 1->2

Chain cycles: 2

Code:

  movi v0.16b, 0
  tbx v0.16b, { v1.16b, v2.16b, v3.16b, v4.16b }, v5.16b
  add v1.16b, v0.16b, v0.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4
  movi v4.16b, 5
  movi v5.16b, 6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 8.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
60204	100033	50101	101	50000	100	50000	300	2549248	50100	200	50004	200	140012	1	60000	100
60204	100033	50101	101	50000	100	50000	300	2549248	50100	200	50004	200	140012	1	60000	100
60204	100033	50101	101	50000	100	50000	300	2549248	50100	200	50004	200	140012	1	60000	100
60205	100066	50111	103	50008	102	50034	300	2549248	50100	200	50004	200	140012	1	60000	100
60204	100033	50101	101	50000	100	50000	300	2549248	50100	200	50004	200	140012	1	60000	100
60204	100033	50101	101	50000	100	50000	300	2549248	50100	200	50004	200	140012	1	60000	100
60205	100066	50109	101	50008	100	50034	300	2549248	50100	200	50004	200	140012	1	60000	100
60205	100066	50109	101	50008	100	50034	201	1708845	33616	134	33561	200	140012	1	60000	100
60204	100033	50101	101	50000	100	50000	300	2549248	50100	200	50004	200	140012	1	60000	100
60204	100033	50101	101	50000	100	50000	300	2549248	50100	200	50004	200	140012	1	60000	100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 8.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
60024	100033	50011	11	50000	10	50000	2036	91876	50587	2549886	55612	5071	2317	50086	20	140012	1	60000	10
60024	100033	50011	11	50000	10	50000	0	30	0	2549248	50010	20	0	50000	20	140000	1	60000	10
60024	100033	50011	11	50000	10	50000	0	30	0	2549248	50010	20	0	50000	20	140000	1	60000	10
60024	100033	50011	11	50000	10	50000	0	34	0	2549580	50045	20	0	50044	20	140000	1	60000	10
60024	100033	50011	11	50000	10	50000	0	30	0	2549248	50010	20	0	50000	20	140000	1	60000	10
60024	100033	50011	11	50000	10	50000	0	30	0	2549248	50010	20	0	50000	20	140000	1	60000	10
60024	100033	50011	11	50000	10	50000	0	30	0	2549248	50010	20	0	50000	20	140000	1	60000	10
60024	100033	50011	11	50000	10	50000	0	30	0	2549248	50010	20	0	50000	20	140000	1	60000	10
60024	100033	50011	11	50000	10	50000	0	30	0	2549248	50010	20	0	50000	20	140000	1	60000	10
60024	100033	50011	11	50000	10	50000	0	30	0	2549248	50010	20	0	50000	20	140000	1	60000	10

Test 4: Latency 1->3

Chain cycles: 2

Code:

  movi v0.16b, 0
  tbx v0.16b, { v1.16b, v2.16b, v3.16b, v4.16b }, v5.16b
  add v2.16b, v0.16b, v0.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4
  movi v4.16b, 5
  movi v5.16b, 6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 6.0035

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
60204	80035	50101	101	50000	100	50000	300	2029271	50100	200	50004	200	140012	1	60000	100
60204	80035	50101	101	50000	100	50000	300	2029274	50100	200	50004	200	140012	1	60000	100
60205	80068	50117	101	50016	100	50042	300	2029567	50142	200	50052	200	140012	1	60000	100
60204	80035	50101	101	50000	100	50000	300	2029277	50100	200	50004	200	140012	1	60000	100
60204	80035	50101	101	50000	100	50000	300	2029277	50100	200	50004	200	140012	1	60000	100
60204	80035	50101	101	50000	100	50000	300	2029277	50100	200	50004	200	140012	1	60000	100
60204	80035	50101	101	50000	100	50000	300	2029277	50100	200	50004	200	140012	1	60000	100
60204	80035	50101	101	50000	100	50000	300	2029277	50100	200	50004	200	140012	1	60000	100
60204	80035	50101	101	50000	100	50000	300	2029277	50100	200	50004	200	140012	1	60000	100
60204	80035	50101	101	50000	100	50000	300	2029277	50100	200	50004	200	140012	1	60000	100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 6.0035

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
60024	80035	50011	11	50000	10	50000	30	2029275	50010	20	50004	20	140012	1	60000	10
60024	80035	50011	11	50000	10	50000	30	2029567	50052	20	50052	20	140000	1	60000	10
60024	80035	50011	11	50000	10	50000	30	2029277	50010	20	50000	20	140000	1	60000	10
60024	80035	50011	11	50000	10	50000	30	2029277	50010	20	50000	20	140000	1	60000	10
60024	80035	50011	11	50000	10	50000	30	2029277	50010	20	50000	20	140000	1	60000	10
60024	80035	50011	11	50000	10	50000	30	2029277	50010	20	50000	20	140000	1	60000	10
60024	80035	50011	11	50000	10	50000	30	2029277	50010	20	50000	20	140000	1	60000	10
60024	80035	50011	11	50000	10	50000	30	2029277	50010	20	50000	20	140000	1	60000	10
60024	80035	50011	11	50000	10	50000	30	2029277	50010	20	50000	20	140000	1	60000	10
60024	80035	50011	11	50000	10	50000	30	2029277	50010	20	50000	20	140000	1	60000	10

Test 5: Latency 1->4

Chain cycles: 2

Code:

  movi v0.16b, 0
  tbx v0.16b, { v1.16b, v2.16b, v3.16b, v4.16b }, v5.16b
  add v3.16b, v0.16b, v0.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4
  movi v4.16b, 5
  movi v5.16b, 6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 4.0037

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
60204	60037	50101	101	50000	100	50000	300	1509251	50100	200	50007	200	140020	1	60000	100
60204	60037	50101	101	50000	100	50000	300	1509285	50100	200	50007	200	140020	1	60000	100
60204	60037	50101	101	50000	100	50000	300	1509285	50100	200	50007	200	140020	1	60000	100
60204	60037	50101	101	50000	100	50000	300	1509285	50100	200	50007	200	140020	1	60000	100
60204	60037	50101	101	50000	100	50000	300	1509285	50100	200	50007	200	140020	1	60000	100
60204	60037	50101	101	50000	100	50000	300	1509285	50100	200	50007	200	140020	1	60000	100
60204	60037	50101	101	50000	100	50000	300	1509285	50100	200	50007	200	140020	1	60000	100
60204	60037	50101	101	50000	100	50000	300	1509285	50100	200	50007	200	140020	1	60000	100
60204	60037	50101	101	50000	100	50000	300	1509285	50100	200	50007	200	140020	1	60000	100
60204	60037	50101	101	50000	100	50000	300	1509285	50100	200	50007	200	140020	1	60000	100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 4.0037

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
60024	60037	50011	11	50000	10	50000	30	1509267	50010	20	50000	20	140000	1	60000	10
60024	60037	50011	11	50000	10	50000	30	1509285	50010	20	50000	20	140000	1	60000	10
60024	60037	50011	11	50000	10	50000	30	1509285	50010	20	50000	20	140000	1	60000	10
60024	60037	50011	11	50000	10	50000	30	1509285	50010	20	50000	20	140000	1	60000	10
60024	60037	50011	11	50000	10	50000	30	1509285	50010	20	50000	20	140000	1	60000	10
60024	60037	50011	11	50000	10	50000	30	1509285	50010	20	50000	20	140000	1	60000	10
60024	60037	50011	11	50000	10	50000	30	1509285	50010	20	50000	20	140174	1	60000	10
60024	60037	50011	11	50000	10	50000	30	1509285	50010	20	50000	20	140000	1	60000	10
60024	60037	50011	11	50000	10	50000	30	1509859	50118	20	50127	20	140188	1	60000	10
60025	60072	50039	11	50028	10	50054	30	1509285	50010	20	50007	20	140020	1	60000	10

Test 6: Latency 1->5

Chain cycles: 2

Code:

  movi v0.16b, 0
  tbx v0.16b, { v1.16b, v2.16b, v3.16b, v4.16b }, v5.16b
  add v4.16b, v0.16b, v0.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4
  movi v4.16b, 5
  movi v5.16b, 6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 2.0039

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
60204	40039	50101	101	50000	100	50003	300	981521	50103	200	50007	200	140020	1	60000	100
60204	40039	50101	101	50000	100	50003	300	981748	50103	200	50007	200	140020	1	60000	100
60204	40039	50101	101	50000	100	50003	300	982055	50178	200	50088	200	140020	1	60000	100
60204	40039	50101	101	50000	100	50003	300	981748	50103	200	50007	200	140020	1	60000	100
60204	40039	50101	101	50000	100	50003	300	981748	50103	200	50007	200	140020	1	60000	100
60204	40039	50101	101	50000	100	50003	300	981748	50103	200	50007	200	140020	1	60000	100
60204	40039	50101	101	50000	100	50003	300	981748	50103	200	50007	200	140020	1	60000	100
60204	40039	50101	101	50000	100	50003	300	982368	50175	200	50085	200	140020	1	60000	100
60204	40039	50101	101	50000	100	50003	300	981748	50103	200	50007	200	140020	1	60000	100
60204	40039	50101	101	50000	100	50003	300	981637	50103	200	50009	200	140020	1	60000	100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 2.0039

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
60024	40039	50011	11	50000	10	50003	30	981513	50010	20	50000	20	140000	1	60000	10
60024	40039	50011	11	50000	10	50000	30	981733	50010	20	50000	20	140000	1	60000	10
60024	40039	50011	11	50000	10	50000	30	981733	50010	20	50000	20	140000	1	60000	10
60024	40039	50011	11	50000	10	50000	30	981733	50010	20	50000	20	140000	1	60000	10
60024	40039	50011	11	50000	10	50000	30	981733	50010	20	50000	20	140000	1	60000	10
60024	40039	50011	11	50000	10	50000	30	981733	50010	20	50000	20	140000	1	60000	10
60024	40039	50011	11	50000	10	50000	30	981733	50010	20	50000	20	140000	1	60000	10
60024	40039	50011	11	50000	10	50000	30	981733	50010	20	50000	20	140000	1	60000	10
60024	40039	50011	11	50000	10	50000	30	981733	50010	20	50000	20	140000	1	60000	10
60024	40039	50011	11	50000	10	50000	30	981733	50010	20	50000	20	140000	1	60000	10

Test 7: Latency 1->6

Chain cycles: 2

Code:

  movi v0.16b, 0
  tbx v0.16b, { v1.16b, v2.16b, v3.16b, v4.16b }, v5.16b
  add v5.16b, v0.16b, v0.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4
  movi v4.16b, 5
  movi v5.16b, 6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 8.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
60204	100033	50101	101	50000	100	50000	300	2549248	50100	200	50004	200	140012	1	60000	100
60204	100033	50101	101	50000	100	50000	300	2549248	50100	200	50004	200	140012	1	60000	100
60204	100033	50101	101	50000	100	50000	300	2549248	50100	200	50004	200	140012	1	60000	100
60204	100033	50101	101	50000	100	50000	300	2549248	50100	200	50004	200	140012	1	60000	100
60204	100033	50101	101	50000	100	50000	300	2549248	50100	200	50004	200	140012	1	60000	100
60205	100067	50109	101	50008	100	50034	300	2549248	50100	200	50004	200	140012	1	60000	100
60204	100033	50101	101	50000	100	50000	300	2549248	50100	200	50004	200	140012	1	60000	100
60204	100033	50101	101	50000	100	50000	300	2549248	50100	200	50004	200	140012	1	60000	100
60204	100033	50101	101	50000	100	50000	300	2549248	50100	200	50004	200	140012	1	60000	100
60204	100033	50101	101	50000	100	50000	300	2549248	50100	200	50004	200	140012	1	60000	100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 8.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
60024	100033	50011	11	50000	0	10	50000	30	2549248	50010	20	50000	20	140000	1	60000	10
60024	100033	50011	11	50000	0	10	50000	30	2549248	50010	20	50000	20	140000	1	60000	10
60024	100033	50011	11	50000	0	10	50000	30	2549248	50010	20	50000	20	140000	1	60000	10
60024	100033	50011	11	50000	0	10	50000	30	2549248	50010	20	50000	20	140000	1	60000	10
73500	128987	61281	7801	48952	4528	7297	49043	30	2549248	50010	20	50000	20	140130	1	60000	10
60024	100033	50011	11	50000	0	10	50000	30	2549248	50010	20	50000	20	140000	1	60000	10
60024	100033	50011	11	50000	0	10	50000	30	2549248	50010	20	50000	20	140000	1	60000	10
60024	100033	50011	11	50000	0	10	50000	30	2549248	50010	20	50000	20	140000	1	60000	10
60024	100033	50011	11	50000	0	10	50000	30	2549248	50010	20	50000	20	140000	1	60000	10
60024	100033	50011	11	50000	0	10	50000	30	2549248	50010	20	50000	20	140000	1	60000	10

Test 8: throughput

Count: 8

Code:

  movi v0.16b, 0
  tbx v0.16b, { v8.16b, v9.16b, v10.16b, v11.16b }, v12.16b
  movi v1.16b, 0
  tbx v1.16b, { v8.16b, v9.16b, v10.16b, v11.16b }, v12.16b
  movi v2.16b, 0
  tbx v2.16b, { v8.16b, v9.16b, v10.16b, v11.16b }, v12.16b
  movi v3.16b, 0
  tbx v3.16b, { v8.16b, v9.16b, v10.16b, v11.16b }, v12.16b
  movi v4.16b, 0
  tbx v4.16b, { v8.16b, v9.16b, v10.16b, v11.16b }, v12.16b
  movi v5.16b, 0
  tbx v5.16b, { v8.16b, v9.16b, v10.16b, v11.16b }, v12.16b
  movi v6.16b, 0
  tbx v6.16b, { v8.16b, v9.16b, v10.16b, v11.16b }, v12.16b
  movi v7.16b, 0
  tbx v7.16b, { v8.16b, v9.16b, v10.16b, v11.16b }, v12.16b

Initialization

  movi v8.16b, 9
  movi v9.16b, 10
  movi v10.16b, 11
  movi v11.16b, 12
  movi v12.16b, 13

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
400204	160089	320101	101	320000	100	320012	0	300	0	3484556	320112	200	0	320015	200	960237	1	400000	100
400204	160047	320101	101	320000	100	320012	0	300	0	3507169	320112	200	0	320015	200	960045	1	400000	100
400206	160128	320181	101	320080	100	320125	0	300	0	3507169	320112	200	0	320015	200	960237	1	400000	100
400205	160092	320142	101	320041	100	320074	0	300	0	3507169	320112	200	0	320015	200	960045	1	400000	100
400204	160047	320101	101	320000	100	320012	0	300	0	2751437	320174	200	0	320079	200	960237	1	400000	100
400206	160128	320180	101	320079	100	320127	0	300	0	3497467	320112	200	0	320015	200	960234	1	400000	100
400204	160047	320101	101	320000	100	320012	0	300	0	3507169	320112	200	0	320015	200	960045	1	400000	100
400204	160047	320101	101	320000	100	320012	0	300	0	3507169	320112	200	0	320015	200	960045	1	400000	100
400204	160047	320101	101	320000	100	320012	0	300	0	3507169	320112	200	0	320015	200	960045	1	400000	100
400205	160089	320143	101	320042	100	320073	0	300	0	3507169	320112	200	0	320015	200	960045	1	400000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
400024	160077	320011	11	320000	10	320012	0	30	0	3295867	320022	20	0	320015	20	0	960045	1	0	400000	10
400024	160047	320011	11	320000	10	320012	0	30	0	3391969	320022	20	0	320015	20	0	960045	1	0	400000	10
400024	160047	320011	11	320000	10	320012	0	30	0	3391969	320022	20	0	320015	20	0	960045	1	0	400000	10
400024	160047	320011	11	320000	10	320012	0	30	0	3391969	320022	20	0	320015	20	0	960045	1	0	400000	10
400024	160047	320011	11	320000	10	320012	0	30	0	3391969	320022	20	0	320015	20	0	960045	1	0	400000	10
400025	160092	320051	11	320040	10	320074	0	30	0	3391969	320022	20	0	320015	20	0	960045	1	0	400000	10
400024	160047	320011	11	320000	10	320012	0	30	0	3391969	320022	20	0	320015	20	0	960045	1	0	400000	10
400024	160047	320011	11	320000	10	320012	0	30	0	3391969	320022	20	0	320015	20	0	960201	1	0	400000	10
400024	160049	320012	11	320001	10	320012	0	30	0	3391969	320022	20	0	320015	20	0	960402	1	0	400000	10
400024	160048	320011	11	320000	10	320012	0	30	0	3391548	320022	20	0	320015	20	0	960045	1	0	400000	10

TBX (four register table, 16B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: Latency 1->4

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: Latency 1->5

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 7: Latency 1->6

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 8: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations