Icestorm: TBX (four register table, 8B) measurements

Code:

  tbx v0.8b, { v1.16b, v2.16b, v3.16b, v4.16b }, v5.8b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4
  movi v4.16b, 5
  movi v5.16b, 6

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 4.000

Issues: 4.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 4.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
4004	8033	4001	1	4000	4000	203248	4000	4000	0	0	12000	1	0	4000	0
4004	8033	4001	1	4000	4000	203248	4000	4000	0	0	12000	1	0	4000	0
4004	8033	4001	1	4000	4000	203248	4000	4000	0	0	12000	1	0	4000	0
4004	8033	4001	1	4000	4000	203248	4000	4000	0	0	12000	1	0	4000	0
4004	8033	4001	1	4000	4000	203248	4000	4000	0	0	12000	1	0	4000	0
4004	8033	4001	1	4000	4000	203248	4000	4000	0	0	12000	1	0	4000	0
4004	8033	4001	1	4000	4000	203248	4000	4000	0	0	12000	1	0	4000	0
4004	8033	4001	1	4000	4000	203248	4000	4000	0	0	12000	1	0	4000	0
4004	8033	4001	1	4000	4000	203248	4000	4000	0	0	12000	1	0	4000	0
4004	8033	4001	1	4000	4000	203248	4000	4000	0	0	12000	1	0	4000	0

Test 2: Latency 1->1

Code:

  tbx v0.8b, { v1.16b, v2.16b, v3.16b, v4.16b }, v5.8b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4
  movi v4.16b, 5
  movi v5.16b, 6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 8.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
40204	80033	40101	101	40000	0	100	40000	300	2039248	40100	200	40008	200	120024	1	40000	100
40204	80033	40101	101	40000	0	100	40000	300	2039248	40100	200	40008	200	120024	1	40000	100
40204	80033	40101	101	40000	0	100	40000	300	2039248	40100	200	40008	200	120024	1	40000	100
40205	80066	40109	101	40008	0	100	40034	300	2039248	40100	200	40008	200	120024	1	40000	100
40204	80033	40101	101	40000	0	100	40000	300	2039248	40100	200	40008	200	120024	1	40000	100
40204	80033	40101	101	40000	0	100	40000	300	2039248	40100	200	40008	200	120024	1	40000	100
40204	80033	40101	101	40000	0	100	40000	300	2039248	40100	200	40008	200	120024	1	40000	100
40204	80033	40101	101	40000	0	100	40000	300	2039248	40100	200	40008	200	120024	1	40000	100
40204	80033	40101	101	40000	0	100	40000	300	2039248	40100	200	40008	200	120024	1	40000	100
40204	80033	40101	101	40000	0	100	40000	300	2039248	40100	200	40008	200	120024	1	40000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 8.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
40024	80033	40011	11	40000	10	40000	30	2039248	40010	20	40008	20	120000	1	40000	10
40024	80033	40011	11	40000	10	40000	30	2039248	40010	20	40000	20	120000	1	40000	10
40024	80033	40011	11	40000	10	40000	30	2039248	40010	20	40000	20	120000	1	40000	10
40024	80033	40011	11	40000	10	40000	30	2039248	40010	20	40000	20	120000	1	40000	10
40024	80033	40011	11	40000	10	40000	30	2039248	40010	20	40000	20	120000	1	40000	10
40024	80033	40011	11	40000	10	40000	30	2039248	40010	20	40000	20	120000	1	40000	10
40024	80033	40011	11	40000	10	40000	30	2039248	40010	20	40000	20	120000	1	40000	10
40024	80033	40011	11	40000	10	40000	30	2039248	40010	20	40000	20	120000	1	40000	10
40024	80033	40011	11	40000	10	40000	30	2039248	40010	20	40000	20	120000	1	40000	10
40024	80033	40011	11	40000	10	40000	30	2039248	40010	20	40000	20	120024	1	40000	10

Test 3: Latency 1->2

Chain cycles: 2

Code:

  movi v0.16b, 0
  tbx v0.8b, { v1.16b, v2.16b, v3.16b, v4.16b }, v5.8b
  add v1.16b, v0.16b, v0.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4
  movi v4.16b, 5
  movi v5.16b, 6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 8.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
60204	100033	50101	101	50000	100	50000	0	300	0	2549580	50134	200	0	50044	200	140012	1	60000	100
60204	100033	50101	101	50000	100	50000	0	300	0	2549248	50100	200	0	50004	200	140012	1	60000	100
60204	100033	50101	101	50000	100	50000	0	300	0	2549248	50100	200	0	50004	200	140012	1	60000	100
60204	100033	50101	101	50000	100	50000	0	300	0	2549248	50100	200	0	50004	200	140012	1	60000	100
60204	100033	50101	101	50000	100	50000	0	300	0	2549248	50100	200	0	50004	200	140012	1	60000	100
60204	100033	50101	101	50000	100	50000	0	300	0	2549248	50100	200	0	50004	200	140012	1	60000	100
60204	100033	50101	101	50000	100	50000	0	300	0	2549248	50100	200	0	50004	200	140012	1	60000	100
60204	100033	50101	101	50000	100	50000	0	300	0	2549580	50134	200	0	50044	200	140012	1	60000	100
60204	100033	50101	101	50000	100	50000	0	300	0	2549248	50100	200	0	50004	200	140012	1	60000	100
60204	100033	50101	101	50000	100	50000	0	300	0	2549580	50134	200	0	50046	200	140012	1	60000	100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 8.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
60024	100033	50011	11	50000	10	50000	30	2549248	50010	20	50000	20	0	140000	1	0	60000	10
60024	100033	50011	11	50000	10	50000	30	2549248	50010	20	50000	20	0	140000	1	0	60000	10
60024	100033	50011	11	50000	10	50000	30	2549248	50010	20	50000	20	0	140000	1	0	60000	10
60024	100033	50011	11	50000	10	50000	30	2549248	50010	20	50000	20	0	140000	1	0	60000	10
60024	100033	50011	11	50000	10	50000	30	2549248	50010	20	50000	20	0	140000	1	0	60000	10
60024	100033	50011	11	50000	10	50000	30	2549248	50010	20	50000	20	0	140000	1	0	60000	10
60024	100033	50011	11	50000	10	50000	30	2549248	50010	20	50004	20	0	140130	1	0	60000	10
60025	100066	50019	11	50008	10	50034	30	2549248	50010	20	50000	20	0	140000	1	0	60000	10
60024	100033	50011	11	50000	10	50000	30	2549248	50010	20	50000	20	0	140000	1	0	60000	10
60024	100033	50011	11	50000	10	50000	30	2549248	50010	20	50000	20	0	140124	1	0	60000	10

Test 4: Latency 1->3

Chain cycles: 2

Code:

  movi v0.16b, 0
  tbx v0.8b, { v1.16b, v2.16b, v3.16b, v4.16b }, v5.8b
  add v2.16b, v0.16b, v0.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4
  movi v4.16b, 5
  movi v5.16b, 6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 6.0035

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
60204	81809	50844	109	50735	108	51560	0	314	0	2046804	51616	204	0	51657	206	144908	4	60000	100
60204	81812	50844	109	50735	108	51560	0	331	0	2051038	51941	210	0	52000	206	145590	4	60000	100
60204	81960	50909	111	50798	110	51692	0	307	0	2049144	51795	202	0	51849	204	145322	3	60000	100
60205	82086	50944	109	50835	108	51782	0	342	0	2049303	51807	212	0	51851	206	144758	4	60000	100
60204	81854	50861	105	50756	104	51601	0	345	0	2046105	51582	214	0	51605	208	144100	5	60000	100
60204	81944	50907	109	50798	108	51684	0	321	0	2046571	51614	206	0	51648	204	145034	3	60000	100
60204	81858	50865	109	50756	108	51602	85878	4176309	2516134	2195008	247261	155251	101990	53238	206	143686	4	60000	100
60204	80902	50460	103	50357	102	50757	0	314	0	2044347	51395	204	0	51411	202	143126	2	60000	100
60204	81001	50506	107	50399	106	50849	0	321	0	2036536	50729	206	0	50683	204	141924	3	60000	100
60204	80897	50462	105	50357	104	50757	0	300	0	2036822	50764	200	0	50731	200	142062	1	60000	100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 6.0035

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
60024	80035	50011	11	50000	10	50000	30	2029275	50010	20	50004	20	0	140012	1	0	60000	10
60024	80035	50011	11	50000	10	50000	34	2029567	50053	20	50052	20	0	140000	1	0	60000	10
60024	80035	50011	11	50000	10	50000	30	2029277	50010	20	50000	20	0	140000	1	0	60000	10
60024	80035	50011	11	50000	10	50000	30	2029277	50010	20	50000	20	0	140000	1	0	60000	10
60024	80035	50011	11	50000	10	50000	30	2029277	50010	20	50000	20	0	140000	1	0	60000	10
60024	80035	50011	11	50000	10	50000	30	2029277	50010	20	50000	20	0	140000	1	0	60000	10
60024	80035	50011	11	50000	10	50000	30	2029277	50010	20	50000	20	0	140000	1	0	60000	10
60024	80035	50011	11	50000	10	50000	30	2029277	50010	20	50000	20	0	140000	1	0	60000	10
60024	80035	50011	11	50000	10	50000	30	2029567	50052	20	50052	20	0	140000	1	0	60000	10
60024	80035	50011	11	50000	10	50000	30	2029277	50010	20	50000	20	0	140000	1	0	60000	10

Test 5: Latency 1->4

Chain cycles: 2

Code:

  movi v0.16b, 0
  tbx v0.8b, { v1.16b, v2.16b, v3.16b, v4.16b }, v5.8b
  add v3.16b, v0.16b, v0.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4
  movi v4.16b, 5
  movi v5.16b, 6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 4.0037

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
60204	60037	50101	101	50000	0	100	50000	300	1509246	50100	200	50007	200	140020	1	60000	100
60204	60037	50101	101	50000	0	100	50000	300	1509285	50100	200	50007	200	140020	1	60000	100
60204	60037	50101	101	50000	0	100	50000	300	1509285	50100	200	50007	200	140020	1	60000	100
60204	60037	50101	101	50000	0	100	50000	300	1509285	50100	200	50007	200	140020	1	60000	100
60204	60037	50101	101	50000	0	100	50000	300	1509285	50100	200	50007	200	140020	1	60000	100
60205	60074	50130	101	50029	0	100	50054	300	1509285	50100	200	50007	200	140020	1	60000	100
60204	60037	50101	101	50000	0	100	50000	300	1509285	50100	200	50007	200	140020	1	60000	100
60204	60037	50101	101	50000	0	100	50000	300	1509285	50100	200	50007	200	140020	1	60000	100
60204	60037	50101	101	50000	0	100	50000	300	1509285	50100	200	50007	200	140020	1	60000	100
60204	60037	50101	101	50000	0	100	50000	300	1509285	50100	200	50007	200	140020	1	60000	100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 4.0037

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
60024	60037	50011	11	50000	10	50000	30	1509268	50010	20	50007	20	140000	1	60000	10
60024	60037	50011	11	50000	10	50000	30	1509285	50010	20	50000	20	140000	1	60000	10
60024	60037	50011	11	50000	10	50000	30	1509285	50010	20	50000	20	140000	1	60000	10
60024	60037	50011	11	50000	10	50000	30	1509285	50010	20	50000	20	140000	1	60000	10
60024	60037	50011	11	50000	10	50000	30	1509285	50010	20	50000	20	140000	1	60000	10
60024	60037	50011	11	50000	10	50000	30	1509285	50010	20	50000	20	140000	1	60000	10
60024	60037	50011	11	50000	10	50000	30	1509285	50010	20	50000	20	140000	1	60000	10
60024	60037	50011	11	50000	10	50000	30	1509285	50010	20	50000	20	140000	1	60000	10
60024	60037	50011	11	50000	10	50000	30	1509285	50010	20	50000	20	140000	1	60000	10
60024	60037	50011	11	50000	10	50000	30	1509285	50010	20	50000	20	140000	1	60000	10

Test 6: Latency 1->5

Chain cycles: 2

Code:

  movi v0.16b, 0
  tbx v0.8b, { v1.16b, v2.16b, v3.16b, v4.16b }, v5.8b
  add v4.16b, v0.16b, v0.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4
  movi v4.16b, 5
  movi v5.16b, 6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 2.0039

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
60204	40039	50101	101	50000	100	50003	300	981475	50104	200	50009	200	140020	1	60000	100
60204	40039	50101	101	50000	100	50003	300	982935	50257	200	50163	200	140026	1	60000	100
60204	40039	50101	101	50000	100	50003	300	981748	50103	200	50007	200	140470	1	60000	100
60204	40039	50101	101	50000	100	50003	300	981748	50103	200	50007	200	140020	1	60000	100
60204	40156	50215	103	50112	102	50156	300	981748	50103	200	50007	200	140020	1	60000	100
60204	40156	50215	101	50114	100	50157	300	981748	50103	200	50007	200	140242	1	60000	100
60204	40039	50101	101	50000	100	50003	300	982747	50259	200	50165	200	140020	1	60000	100
60204	40039	50101	101	50000	100	50003	300	982609	50261	200	50167	202	140680	2	60000	100
60204	40217	50272	103	50169	102	50234	300	982910	50337	200	50243	200	140230	1	60000	100
60204	40039	50101	101	50000	100	50003	300	981748	50103	200	50007	200	140020	1	60000	100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 2.0039

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
60024	40039	50012	11	50001	10	50004	30	981733	50010	20	50000	20	140000	1	60000	10
60024	40039	50011	11	50000	10	50000	30	981733	50010	20	50000	20	140000	1	60000	10
60024	40039	50011	11	50000	10	50000	30	981733	50010	20	50000	20	140000	1	60000	10
60024	40039	50011	11	50000	10	50000	30	981733	50010	20	50000	20	140000	1	60000	10
60024	40039	50011	11	50000	10	50000	30	981733	50010	20	50000	20	140000	1	60000	10
60024	40039	50011	11	50000	10	50000	30	981733	50010	20	50000	20	140000	1	60000	10
60024	40039	50011	11	50000	10	50000	30	981733	50010	20	50000	20	140000	1	60000	10
60024	40039	50011	11	50000	10	50000	30	981733	50010	20	50000	20	140000	1	60000	10
60024	40039	50011	11	50000	10	50003	30	981513	50010	20	50000	20	140000	1	60000	10
60024	40039	50011	11	50000	10	50000	30	981733	50010	20	50000	20	140000	1	60000	10

Test 7: Latency 1->6

Chain cycles: 2

Code:

  movi v0.16b, 0
  tbx v0.8b, { v1.16b, v2.16b, v3.16b, v4.16b }, v5.8b
  add v5.16b, v0.16b, v0.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4
  movi v4.16b, 5
  movi v5.16b, 6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 8.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
60205	100066	50109	101	50008	100	50034	300	2549248	50100	200	50004	200	0	140012	1	0	60000	100
60204	100033	50101	101	50000	100	50000	300	2549248	50100	200	50004	200	0	140012	1	0	60000	100
60204	100033	50101	101	50000	100	50000	300	2549248	50100	200	50004	200	0	140012	1	0	60000	100
60204	100033	50101	101	50000	100	50000	300	2549248	50100	200	50004	200	0	140012	1	0	60000	100
60204	100033	50101	101	50000	100	50000	300	2549248	50100	200	50004	200	0	140012	1	0	60000	100
60204	100033	50101	101	50000	100	50000	307	2549580	50136	202	50044	200	0	140124	1	0	60000	100
60204	100033	50101	101	50000	100	50000	300	2549248	50100	200	50004	200	0	140012	1	0	60000	100
60204	100033	50101	101	50000	100	50000	300	2549248	50100	200	50004	200	0	140012	1	0	60000	100
60204	100033	50101	101	50000	100	50000	300	2549248	50100	200	50004	200	0	140012	1	0	60000	100
60204	100033	50101	101	50000	100	50000	300	2549248	50100	200	50004	200	0	140012	1	0	60000	100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 8.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
60024	100033	50011	11	50000	0	10	50000	30	2549248	50010	20	50000	20	140000	1	60000	10
60026	100099	50027	11	50016	0	10	50068	30	2549248	50010	20	50000	20	140000	1	60000	10
60024	100033	50011	11	50000	0	10	50000	30	2549248	50010	20	50000	20	140000	1	60000	10
60024	100033	50011	11	50000	0	10	50000	30	2549248	50010	20	50000	20	140000	1	60000	10
60024	100033	50011	11	50000	0	10	50000	30	2549248	50010	20	50000	20	140000	1	60000	10
60024	100033	50011	11	50000	0	10	50000	30	2549248	50010	20	50000	20	140000	1	60000	10
60024	100033	50011	11	50000	0	10	50000	30	2549248	50010	20	50000	20	140000	1	60000	10
60024	100033	50011	11	50000	0	10	50000	30	2549248	50010	20	50000	20	140000	1	60000	10
60024	100033	50011	11	50000	0	10	50000	30	2549248	50010	20	50000	20	140000	1	60000	10
60025	100066	50019	11	50008	0	10	50034	30	2549248	50010	20	50000	20	140000	1	60000	10

Test 8: throughput

Count: 8

Code:

  movi v0.16b, 0
  tbx v0.8b, { v8.16b, v9.16b, v10.16b, v11.16b }, v12.8b
  movi v1.16b, 0
  tbx v1.8b, { v8.16b, v9.16b, v10.16b, v11.16b }, v12.8b
  movi v2.16b, 0
  tbx v2.8b, { v8.16b, v9.16b, v10.16b, v11.16b }, v12.8b
  movi v3.16b, 0
  tbx v3.8b, { v8.16b, v9.16b, v10.16b, v11.16b }, v12.8b
  movi v4.16b, 0
  tbx v4.8b, { v8.16b, v9.16b, v10.16b, v11.16b }, v12.8b
  movi v5.16b, 0
  tbx v5.8b, { v8.16b, v9.16b, v10.16b, v11.16b }, v12.8b
  movi v6.16b, 0
  tbx v6.8b, { v8.16b, v9.16b, v10.16b, v11.16b }, v12.8b
  movi v7.16b, 0
  tbx v7.8b, { v8.16b, v9.16b, v10.16b, v11.16b }, v12.8b

Initialization

  movi v8.16b, 9
  movi v9.16b, 10
  movi v10.16b, 11
  movi v11.16b, 12
  movi v12.16b, 13

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
400205	160116	320141	101	320040	0	100	320074	300	3497467	320112	200	320015	200	960234	1	400000	100
400204	160060	320102	101	320001	0	100	320012	300	3507169	320112	200	320015	200	960045	1	400000	100
400204	160047	320101	101	320000	0	100	320012	300	3507169	320112	200	320015	200	960045	1	400000	100
400204	160047	320101	101	320000	0	100	320012	300	3507169	320112	200	320015	200	960045	1	400000	100
400204	160047	320101	101	320000	0	100	320012	300	3507169	320112	200	320015	200	960045	1	400000	100
400204	160047	320101	101	320000	0	100	320012	300	3507169	320112	200	320015	200	960045	1	400000	100
400204	160047	320101	101	320000	0	100	320012	300	3507169	320112	200	320015	200	960045	1	400000	100
400204	160047	320101	101	320000	0	100	320012	300	3507169	320112	200	320015	200	960045	1	400000	100
400204	160074	320101	101	320000	0	100	320012	300	3507169	320112	200	320015	200	960045	1	400000	100
400204	160047	320101	101	320000	0	100	320012	300	3507169	320112	200	320015	200	960045	1	400000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
400024	160079	320011	11	320000	0	10	320012	0	30	0	3295867	320022	20	0	320015	20	960000	1	400000	10
400024	160047	320011	11	320000	0	10	320000	0	30	0	3391889	320010	20	0	320000	20	960000	1	400000	10
400024	160047	320011	11	320000	0	10	320000	0	30	0	2672344	320077	20	0	320070	20	960000	1	400000	10
400024	160047	320011	11	320000	0	10	320000	0	30	0	3391889	320010	20	0	320000	20	960000	1	400000	10
400024	160047	320011	11	320000	0	10	320000	0	30	0	3391889	320010	20	0	320000	20	960000	1	400000	10
400024	160047	320011	11	320000	0	10	320000	0	30	0	3391889	320010	20	0	320000	20	960000	1	400000	10
400024	160047	320011	11	320000	0	10	320000	0	30	0	3391889	320010	20	0	320000	20	960000	1	400000	10
400025	160087	320054	11	320043	0	10	320074	0	30	0	2294797	320084	20	0	320079	20	960000	1	400000	10
400024	160047	320011	11	320000	0	10	320000	0	30	0	3391889	320010	20	0	320000	20	960234	1	400000	10
400024	160047	320011	11	320000	0	10	320000	0	30	0	2644737	320082	20	0	320078	20	960045	1	400000	10

TBX (four register table, 8B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: Latency 1->4

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: Latency 1->5

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 7: Latency 1->6

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 8: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations