Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

TBX (single register table, 16B)

Test 1: uops

Code:

  tbx v0.16b, { v1.16b }, v2.16b
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)
1004203310011100010005024810001000300011000
1004203310011100010005024810001000300011000
1004203310011100010005024810001000300011000
1004203310011100010005024810001000300011000
1004203310011100010005024810001000300011000
1004203310011100010005024810001000300011000
1004203310011100010005024810001000300011000
1004203310011100010005024810001000300011000
1004203310011100010005024810001000300011000
1004203310011100010005024810001000300011000

Test 2: Latency 1->1

Code:

  tbx v0.16b, { v1.16b }, v2.16b
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020420033101011011000010010000300509248101002001000420030012110000100
1020420033101011011000010010000300509248101002001000420030012110000100
1020420033101011011000010010000300509248101002001000420030012110000100
1020420033101011011000010010000300509248101002001000420030012110000100
1020420033101011011000010010000300509580101342001004420030012110000100
1020420033101011011000010010000300509248101002001000420030012110000100
1020420033101011011000010010000300509248101002001000420030012110000100
1020420033101011011000010010000300509248101002001000420030012110000100
1020420033101011011000010010000300509248101002001000420030012110000100
1020420033101011011000010010000300509248101002001000420030012110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024200331002121100002010000705092461002020100042030000111000010
10024200331002121100002010000705092481002020100002030000111000010
10024200861003523100122210036705092481002020100002030000111000010
10024200331002121100002010000705097801005620100422030000111000010
10024200331002121100002010000705092481002020100002030000111000010
10024200331002121100002010000705092481002020100002030123111000010
10024200331002121100002010000705092481002020100002030000111000010
10024200331002121100002010000705092481002020100002030000111000010
10024200851003321100122010036705092481002020100002030000111000010
10024200331002121100002010000705092481002020100002030243111000010

Test 3: Latency 1->2

Code:

  tbx v0.16b, { v0.16b }, v1.16b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020420033101011011000010010000300509248101002001000620030018110000100
1020420033101011011000010010000300509248101002001000420030012110000100
1020420033101011011000010010000300509248101002001000420030012110000100
1020420033101011011000010010000300509580101342001004820030012110000100
1020420033101011011000010010000300509248101002001000420030012110000100
1020420033101011011000010010000300509248101002001000420030012110000100
1020420033101011011000010010000300509248101002001000620030012110000100
1020420033101011011000010010000300509248101002001000420030012110000100
1020420033101011011000010010000300509248101002001000420030012110000100
1020420033101011011000010010000300509248101002001000420030012110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024200331002121100002010000705092471002020100062030000111000010
10024200331002121100002010000705092481002020100002030000111000010
10024200331002121100002010000705092481002020100002030000111000010
10024200331002121100002010000705092481002020100002030000111000010
10024200331002121100002010000705092481002020100002030000111000010
10024200331002121100002010000655095801005420100472030000111000010
10024200331002121100002010000705092481002020100002030000111000010
10024200331002121100002010000705092481002020100002030000111000010
10024200331002121100002010000705092481002020100002030000111000010
10024200331002121100002010000705092481002020100002030000111000010

Test 4: Latency 1->3

Code:

  tbx v0.16b, { v1.16b }, v0.16b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020420033101011011000010010000300509248101002001000420030018110000100
1020420033101011011000010010000300509248101002001000420030018110000100
1020420033101011011000010010000300509248101002001000420030012110000100
1020420033101011011000010010000300509248101002001000420030012110000100
1020420033101011011000010010000300509248101002001000420030012110000100
1020420033101011011000010010000300509248101002001000420030012110000100
1020420033101011011000010010000300509248101002001000420030012110000100
1020420033101011011000010010000300509248101002001000420030012110000100
1020420033101011011000010010000300509248101002001000420030012110000100
1020420033101011011000010010000300509248101002001000420030012110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
100242003310021211000002010000705092471002020100062030018111000010
100242003310021211000002010000705092481002020100002030000111000010
100242003310021211000002010000705092481002020100002030000111000010
100242003310021211000002010000705092481002020100002030000111000010
100252007310029211000802010034705092481002020100002030000111000010
100242003310021211000002010000705092481002020100002030000111000010
100242003310021211000002010000705092481002020100002030144111000010
100242003310021211000002010000705092481002020100002030000111000010
100242003310021211000002010000705092481002020100002030000111000010
100242003310021211000002010000705092481002020100002030000111000010

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  tbx v0.16b, { v8.16b }, v9.16b
  movi v1.16b, 0
  tbx v1.16b, { v8.16b }, v9.16b
  movi v2.16b, 0
  tbx v2.16b, { v8.16b }, v9.16b
  movi v3.16b, 0
  tbx v3.16b, { v8.16b }, v9.16b
  movi v4.16b, 0
  tbx v4.16b, { v8.16b }, v9.16b
  movi v5.16b, 0
  tbx v5.16b, { v8.16b }, v9.16b
  movi v6.16b, 0
  tbx v6.16b, { v8.16b }, v9.16b
  movi v7.16b, 0
  tbx v7.16b, { v8.16b }, v9.16b
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1602044051080109101800081008001230032005680113200800132002400391160000100
1602044009680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032020080149200800492002400361160000100
1602044011080110101800091008001330032005280112200800122002400361160000100
1602044009880109101800081008001230032005280112200800122002400361160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5092

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1600244478080335118032410803283032190880486208047620241365116000010
1600244256180511118050010805003632206080527228051520240963116000010
1600244203980602118059110805913032253680644208063420241689116000010
1600244197380607118059610805963032311280788208077820242019116000010
1600244214480654118064310806433032241680614208060420242112116000010
1600244218180682118067110806713032223280568208055820241812116000010
1600244201780609118059810805983032241680614208060420241674116000010
1600244209480659118064810806483032250880637208062720241800116000010
1600244198180573118056210805623032244880622208061220241794116000010
1600244216680662118065110806513032247680629208061920242118116000010

Test 6: throughput

Count: 16

Code:

  tbx v0.16b, { v16.16b }, v17.16b
  tbx v1.16b, { v16.16b }, v17.16b
  tbx v2.16b, { v16.16b }, v17.16b
  tbx v3.16b, { v16.16b }, v17.16b
  tbx v4.16b, { v16.16b }, v17.16b
  tbx v5.16b, { v16.16b }, v17.16b
  tbx v6.16b, { v16.16b }, v17.16b
  tbx v7.16b, { v16.16b }, v17.16b
  tbx v8.16b, { v16.16b }, v17.16b
  tbx v9.16b, { v16.16b }, v17.16b
  tbx v10.16b, { v16.16b }, v17.16b
  tbx v11.16b, { v16.16b }, v17.16b
  tbx v12.16b, { v16.16b }, v17.16b
  tbx v13.16b, { v16.16b }, v17.16b
  tbx v14.16b, { v16.16b }, v17.16b
  tbx v15.16b, { v16.16b }, v17.16b
  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
160204800441601071011600061001600103006400441601102001600142004800421160000100
160204800441601071011600061001600103006400361601082001600122004800361160000100
160204800341601051011600041001600083006400361601082001600122004800361160000100
160204800341601051011600041001600083006400361601082001600122004800361160000100
160204800341601051011600041001600083006400361601082001600122004800361160000100
160204800341601051011600041001600083006400361601082001600122004800361160000100
160204800341601051011600041001600083076402081601562021600632004801801160000100
160204800361601081011600071001600113006400441601102001600142004800421160000100
160204800341601051011600041001600083006400361601082001600122004800361160000100
160204800341601051011600041001600083006400361601082001600122004800361160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
160024801471600181116000710160011306400441600202016001420480000116000010
160024800521600111116000010160000306400001600102016000020480000116000010
160024800341600111116000010160000306400001600102016000020480000116000010
160024800341600111116000010160000306400001600102016000020480000116000010
160025800691600531116004210160054306400001600102016000020480000116000010
160024800341600111116000010160000306400001600102016000020480000116000010
160024800341600111116000010160000306400001600102016000020480000116000010
160024800341600111116000010160000306400001600102016000020480000116000010
160024800341600111116000010160000306400001600102016000020480000116000010
160024800341600111116000010160000306400001600102016000020480177116000010