Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

TBX (single register table, 8B)

Test 1: uops

Code:

  tbx v0.8b, { v1.16b }, v2.8b
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)
1004203310011100010005024810001000300011000
1004203310011100010005024810001000300011000
1004203310011100010005024810001000300011000
1004203310011100010005024810001000300011000
1004203310011100010005024810001000300011000
1004203310011100010005024810001000300011000
1004203310011100010005024810001000300011000
1004203310011100010005024810001000300011000
1004203310011100010005024810001000300011000
1004203310011100010005024810001000300011000

Test 2: Latency 1->1

Code:

  tbx v0.8b, { v1.16b }, v2.8b
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10204200331010110110000010010000300509248101002001000420030012110000100
10204200331010110110000010010000300509248101002001000420030012110000100
10204200331010110110000010010000300509248101002001000420030012110000100
10205200661010910110008010010034307509580101362021005020030018110000100
14387248151306232788050173430288076300509248101002001000420030012110000100
10204200331010110110000010010000300509248101002001000420030012110000100
10204200331010110110000010010000300509248101002001000420030012110000100
10204200331010110110000010010000300509248101002001000420030012110000100
10204200331010110110000010010000300509248101002001000420030012110000100
10204200331010110110000010010000300509248101002001000420030012110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024200331002121100002010000705092461002020100042030000111000010
10024200331002121100002010000705092481002020100002030000111000010
10024200331002121100002010000705092481002020100002030000111000010
10024200331002121100002010000705092481002020100002030000111000010
10024200331002121100002010000705092481002020100002030000111000010
10024200331002121100002010000705092481002020100002030000111000010
10024200331002121100002010000705092481002020100002030000111000010
10024200331002121100002010000705092481002020100002030000111000010
10024200331002121100002010000705092481002020100002030000111000010
10024200331002121100002010000705092481002020100002030000111000010

Test 3: Latency 1->2

Code:

  tbx v0.8b, { v0.16b }, v1.8b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020420033101011011000010010000300509248101002001000620030012110000100
1020420033101011011000010010000300509248101002001000620030012110000100
1020420033101011011000010010000300509248101002001000420030012110000100
1020420033101011011000010010000300509248101002001000420030012110000100
1020420033101011011000010010000300509248101002001000420030012110000100
1020420033101011011000010010000300509248101002001000420030012110000100
1020420033101011011000010010000300509248101002001000420030012110000100
1020420033101011011000010010000300509248101002001000420030012110000100
1020420033101011011000010010000300509248101002001000420030012110000100
1020420033101011011000010010000300509248101002001000420030012110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
100242003310021211000002010000705092471002020100062030000111000010
100242024110069211004802010144705092481002020100002030000111000010
100242003310021211000002010000705092481002020100002030000111000010
100242003310021211000002010000705092481002020100002030000111000010
100242003310021211000002010000705092481002020100002030000111000010
100242003310021211000002010000705092481002020100002030000111000010
100242003310021211000002010000705092481002020100002030000111000010
100242003310021211000002010000705092481002020100002030249111000010
100242003310021211000002010000705092481002020100002030000111000010
100242003310021211000002010000705092481002020100002030000111000010

Test 4: Latency 1->3

Code:

  tbx v0.8b, { v1.16b }, v0.8b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020420033101011011000010010000300509248101002001000420030138110000100
1020420033101011011000010010000300509248101002001000620030018110000100
1020420033101011011000010010000300509248101002001000420030012110000100
1020420033101011011000010010000300509248101002001000420030012110000100
1020420033101011011000010010000300509248101002001000420030012110000100
1020420033101011011000010010000300509248101002001000420030012110000100
1020420033101011011000010010000300509248101002001000420030012110000100
1020420033101011011000010010000300509580101342001004420030012110000100
1020420033101011011000010010000300509248101002001000420030012110000100
1020420033101011011000010010000300509580101342001004420030012110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024200331002121100002010000705092471002020100002030144111000010
10024200331002121100002010000705092481002020100002030000111000010
10024200331002121100002010000705092481002020100002030000111000010
10024200331002121100002010000705092481002020100002030000111000010
10024200331002121100002010000705092481002020100002030000111000010
10024200331002121100002010000705092481002020100002030000111000010
10024200331002121100002010000705092481002020100002030000111000010
10024200331002121100002010000705092481002020100002030000111000010
10024200331002121100002010000705092481002020100002030000111000010
10024200331002121100002010000705092481002020100002030000111000010

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  tbx v0.8b, { v8.16b }, v9.8b
  movi v1.16b, 0
  tbx v1.8b, { v8.16b }, v9.8b
  movi v2.16b, 0
  tbx v2.8b, { v8.16b }, v9.8b
  movi v3.16b, 0
  tbx v3.8b, { v8.16b }, v9.8b
  movi v4.16b, 0
  tbx v4.8b, { v8.16b }, v9.8b
  movi v5.16b, 0
  tbx v5.8b, { v8.16b }, v9.8b
  movi v6.16b, 0
  tbx v6.8b, { v8.16b }, v9.8b
  movi v7.16b, 0
  tbx v7.8b, { v8.16b }, v9.8b
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1602044044880109101800081008001230032005680113200800132002400361160000100
1602044010880110101800091008001330032005280112200800122002400391160000100
1602044009880109101800081008001230032005680113200800132002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044009680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5052

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1600244409780019118000810800123032005680023208001320240000116000010
1600244123980011118000010800003032000080010208000020240000116000010
1600244040880011118000010800003032000080010208000020240000116000010
1600244037880011118000010800003032000080010208000020240000116000010
1600244040280011118000010800003032000080010208000020240000116000010
1600244040080011118000010800003032000080010208000020240000116000010
1600244039580011118000010800003032000080010208000020240000116000010
1600244042780011118000010800003032000080010208000020240000116000010
1600244039680011118000010800003032000080010208000020240000116000010
1600244043180011118000010800003032000080010208000020240000116000010

Test 6: throughput

Count: 16

Code:

  tbx v0.8b, { v16.16b }, v17.8b
  tbx v1.8b, { v16.16b }, v17.8b
  tbx v2.8b, { v16.16b }, v17.8b
  tbx v3.8b, { v16.16b }, v17.8b
  tbx v4.8b, { v16.16b }, v17.8b
  tbx v5.8b, { v16.16b }, v17.8b
  tbx v6.8b, { v16.16b }, v17.8b
  tbx v7.8b, { v16.16b }, v17.8b
  tbx v8.8b, { v16.16b }, v17.8b
  tbx v9.8b, { v16.16b }, v17.8b
  tbx v10.8b, { v16.16b }, v17.8b
  tbx v11.8b, { v16.16b }, v17.8b
  tbx v12.8b, { v16.16b }, v17.8b
  tbx v13.8b, { v16.16b }, v17.8b
  tbx v14.8b, { v16.16b }, v17.8b
  tbx v15.8b, { v16.16b }, v17.8b
  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
160204800861601051011600041001600083006401921601502001600582004800421160000100
160204800341601071011600061001600103006400361601082001600122004800361160000100
160204800341601051011600041001600083006400361601082001600122004800361160000100
160204800341601051011600041001600083006400361601082001600122004800361160000100
160204800341601051011600041001600083006400361601082001600122004800361160000100
160204800341601051011600041001600083006400361601082001600122004800361160000100
160204800341601051011600041001600083006400361601082001600122004800361160000100
160204800341601051011600041001600083006403641601962001601102004800361160000100
160204800341601051011600041001600083006400361601082001600122004800361160000100
160204800341601051011600041001600083006400361601082001600122004800361160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
16002480165160018111600071016001130640000160010201600002004800001016000010
160024800351600111116000010160000306402081600642016006330582756480210155713511600382240
16002480034160011111600001016000030640000160010201600002004800001016000010
16002480034160011111600001016000030640000160010201600002004800001016000010
16002480034160011111600001016000030640000160010201600002004800001016000010
16002480034160011111600001016000030640000160010201600002004800001016000010
16002480034160011111600001016000030640000160010201600002004800001016000010
16002480034160011111600001016000030640000160010201600002004800001016000010
16002480034160011111600001016000030640000160010201600002004800001016000010
16002480034160011111600001016000030640000160010201600002004800001016000010