Icestorm: TBX (three register table, 16B) measurements

Code:

  tbx v0.16b, { v1.16b, v2.16b, v3.16b }, v4.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4
  movi v4.16b, 5

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 3.000

Issues: 3.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 3.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
3004	6033	3001	1	3000	3000	152248	3000	3000	9000	1	3000
3004	6033	3001	1	3000	3000	152248	3000	3000	9000	1	3000
3004	6033	3001	1	3000	3000	152248	3000	3000	9000	1	3000
3004	6033	3001	1	3000	3000	152248	3000	3000	9000	1	3000
3004	6033	3001	1	3000	3000	152248	3000	3000	9000	1	3000
3004	6033	3001	1	3000	3000	152248	3000	3000	9000	1	3000
3004	6033	3001	1	3000	3000	152248	3000	3000	9000	1	3000
3004	6033	3001	1	3000	3000	152248	3000	3000	9000	1	3000
3004	6033	3001	1	3000	3000	152248	3000	3000	9000	1	3000
3004	6033	3001	1	3000	3000	152248	3000	3000	9000	1	3000

Test 2: Latency 1->1

Code:

  tbx v0.16b, { v1.16b, v2.16b, v3.16b }, v4.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4
  movi v4.16b, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 6.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
30204	60033	30201	201	30000	200	30000	700	1529247	30200	200	30006	200	90012	101	30000	100
30204	60033	30201	201	30000	200	30000	700	1529247	30200	200	30006	200	90012	101	30000	100
30204	60033	30201	201	30000	200	30000	700	1529248	30200	200	30004	200	90144	100	30000	100
30204	60033	30201	201	30000	200	30000	700	1529248	30200	200	30004	200	90012	101	30000	100
30204	60033	30201	201	30000	200	30000	700	1529248	30200	200	30004	200	90012	101	30000	100
30204	60033	30201	201	30000	200	30000	700	1529248	30200	200	30004	200	90012	101	30000	100
30204	60033	30201	201	30000	200	30000	700	1529248	30200	200	30004	200	90012	101	30000	100
30204	60033	30201	201	30000	200	30000	700	1529248	30200	200	30004	200	90012	101	30000	100
30204	60033	30201	201	30000	200	30000	700	1529248	30200	200	30004	200	90012	101	30000	100
30204	60033	30201	201	30000	200	30000	700	1529580	30234	200	30048	200	90012	101	30000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 6.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
30024	60033	30011	11	30000	10	30000	30	1529248	30010	20	30000	20	0	90000	1	0	30000	10
30024	60033	30011	11	30000	10	30000	30	1529248	30010	20	30000	20	0	90000	1	0	30000	10
30024	60033	30011	11	30000	10	30000	30	1529248	30010	20	30000	20	0	90000	1	0	30000	10
30024	60033	30011	11	30000	10	30000	30	1529248	30010	20	30000	20	0	90000	1	0	30000	10
30024	60033	30011	11	30000	10	30000	30	1529248	30010	20	30000	20	0	90000	1	0	30000	10
30024	60033	30011	11	30000	10	30000	30	1529248	30010	20	30000	20	0	90000	1	0	30000	10
30024	60033	30011	11	30000	10	30000	30	1529248	30010	20	30000	20	0	90000	1	0	30000	10
30024	60033	30011	11	30000	10	30000	30	1529248	30010	20	30000	20	0	90000	1	0	30000	10
30024	60033	30011	11	30000	10	30000	30	1529248	30010	20	30000	20	0	90000	1	0	30000	10
30024	60033	30011	11	30000	10	30000	30	1529248	30010	20	30000	20	0	90000	1	0	30000	10

Test 3: Latency 1->2

Chain cycles: 2

Code:

  movi v0.16b, 0
  tbx v0.16b, { v1.16b, v2.16b, v3.16b }, v4.16b
  add v1.16b, v0.16b, v0.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4
  movi v4.16b, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 6.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
50205	80066	40109	101	40008	100	40034	300	2039248	40100	200	40003	200	110009	1	50000	100
50204	80033	40101	101	40000	100	40000	300	2039248	40100	200	40003	200	110009	1	50000	100
50204	80033	40101	101	40000	100	40000	300	2039248	40100	200	40003	200	110009	1	50000	100
50204	80033	40101	101	40000	100	40000	300	2039248	40100	200	40003	200	110009	1	50000	100
50204	80033	40101	101	40000	100	40000	300	2039248	40100	200	40003	200	110009	1	50000	100
50204	80033	40101	101	40000	100	40000	300	2039248	40100	200	40003	200	110009	1	50000	100
50204	80033	40101	101	40000	100	40000	300	2039248	40100	200	40003	200	110009	1	50000	100
50204	80033	40101	101	40000	100	40000	300	2039248	40100	200	40003	200	110009	1	50000	100
50204	80033	40101	101	40000	100	40000	300	2039580	40134	200	40044	200	110124	1	50000	100
50204	80033	40101	101	40000	100	40000	300	2039248	40100	200	40003	200	110011	1	50000	100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 6.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
50024	80232	40059	11	40048	0	10	40144	0	30	0	2039248	40010	20	0	40000	20	0	110000	1	0	50000	10
50024	80033	40011	11	40000	0	10	40000	0	30	0	2039248	40010	20	0	40000	20	0	110000	1	0	50000	10
50024	80033	40011	11	40000	0	10	40000	0	30	0	2039248	40010	20	0	40000	20	0	110000	1	0	50000	10
50024	80234	40059	11	40048	0	10	40144	0	30	0	2039248	40010	20	0	40000	20	0	110000	1	0	50000	10
50024	80033	40011	11	40000	0	10	40000	0	30	0	2039248	40010	20	0	40000	20	0	110000	1	0	50000	10
50024	80033	40011	11	40000	0	10	40000	0	30	0	2039248	40010	20	0	40000	20	0	110000	1	0	50000	10
50024	80033	40011	11	40000	0	10	40000	0	30	0	2039248	40010	20	0	40000	20	0	110000	1	0	50000	10
50024	80033	40011	11	40000	0	10	40000	0	30	0	2039248	40010	20	0	40000	20	0	110000	1	0	50000	10
50024	80033	40011	11	40000	0	10	40000	0	30	0	2039248	40010	20	0	40000	20	0	110000	1	0	50000	10
50024	80230	40059	11	40048	0	10	40144	0	30	0	2039248	40010	20	0	40000	20	0	110000	1	0	50000	10

Test 4: Latency 1->3

Chain cycles: 2

Code:

  movi v0.16b, 0
  tbx v0.16b, { v1.16b, v2.16b, v3.16b }, v4.16b
  add v2.16b, v0.16b, v0.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4
  movi v4.16b, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 4.0035

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
50204	60035	40101	101	40000	100	40000	300	1519240	40100	200	40008	200	110017	1	50000	100
50204	60035	40101	101	40000	100	40000	300	1519254	40100	200	40006	200	110017	1	50000	100
50204	60035	40101	101	40000	100	40000	300	1519254	40100	200	40006	200	110017	1	50000	100
50204	60035	40101	101	40000	100	40000	300	1519254	40100	200	40006	200	110017	1	50000	100
50204	60035	40101	101	40000	100	40000	300	1519254	40100	200	40006	200	110017	1	50000	100
50204	60035	40101	101	40000	100	40000	300	1519254	40100	200	40006	200	110017	1	50000	100
50204	60035	40101	101	40000	100	40000	300	1519254	40100	200	40006	200	110017	1	50000	100
50204	60035	40101	101	40000	100	40000	300	1519254	40100	200	40006	200	110017	1	50000	100
50204	60035	40101	101	40000	100	40000	300	1519254	40100	200	40006	200	110017	1	50000	100
50204	60035	40101	101	40000	100	40000	300	1519254	40100	200	40006	200	110017	1	50000	100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 4.0035

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
50024	60035	40011	11	40000	10	40000	0	30	0	1519250	40010	20	0	40006	20	110000	1	50000	10
50024	60035	40011	11	40000	10	40000	0	30	0	1519254	40010	20	0	40000	20	110000	1	50000	10
50024	60035	40011	11	40000	10	40000	0	30	0	1519254	40010	20	0	40000	20	110000	1	50000	10
50024	60035	40011	11	40000	10	40000	0	34	0	1519581	40056	20	0	40055	20	110000	1	50000	10
50024	60035	40011	11	40000	10	40000	0	30	0	1519254	40010	20	0	40000	20	110000	1	50000	10
50024	60035	40011	11	40000	10	40000	0	30	0	1519254	40010	20	0	40000	20	110000	1	50000	10
50024	60035	40011	11	40000	10	40000	0	30	0	1519254	40010	20	0	40000	20	110000	1	50000	10
50024	60035	40011	11	40000	10	40000	0	30	0	1519254	40010	20	0	40000	20	110000	1	50000	10
50024	60035	40011	11	40000	10	40000	0	30	0	1519254	40010	20	0	40000	20	110000	1	50000	10
50024	60035	40011	11	40000	10	40000	0	30	0	1519254	40010	20	0	40000	20	110000	1	50000	10

Test 5: Latency 1->4

Chain cycles: 2

Code:

  movi v0.16b, 0
  tbx v0.16b, { v1.16b, v2.16b, v3.16b }, v4.16b
  add v3.16b, v0.16b, v0.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4
  movi v4.16b, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 2.0037

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
50204	40037	40101	101	40000	100	40001	0	300	0	999197	40102	200	0	40008	200	110017	1	50000	100
50204	40037	40101	101	40000	100	40001	0	300	0	999270	40101	200	0	40006	200	110017	1	50000	100
50204	40037	40101	101	40000	100	40001	0	300	0	999270	40101	200	0	40006	200	110017	1	50000	100
50204	40037	40101	101	40000	100	40001	0	300	0	999270	40101	200	0	40006	200	110017	1	50000	100
50205	40074	40140	101	40039	100	40066	0	300	0	999270	40101	200	0	40006	200	110017	1	50000	100
50204	40037	40101	101	40000	100	40001	0	300	0	999270	40101	200	0	40006	200	110017	1	50000	100
50204	40037	40101	101	40000	100	40001	0	300	0	999270	40101	200	0	40006	200	110017	1	50000	100
50205	40074	40139	101	40038	100	40064	1585	159895	38055	1001206	44551	3968	1855	40088	200	110022	1	50000	100
50204	40037	40101	101	40000	100	40002	0	300	0	999270	40101	200	0	40006	200	110017	1	50000	100
50204	40037	40101	101	40000	100	40001	0	300	0	999270	40101	200	0	40006	200	110017	1	50000	100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 2.0037

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
50024	40037	40011	11	40000	10	40001	30	999229	40010	20	40000	20	110000	1	50000	10
50024	40037	40011	11	40000	10	40000	30	999265	40010	20	40000	20	110000	1	50000	10
50024	40037	40011	11	40000	10	40000	30	999265	40010	20	40000	20	110000	1	50000	10
50024	40037	40011	11	40000	10	40000	30	999265	40010	20	40000	20	110000	1	50000	10
50024	40037	40011	11	40000	10	40000	30	999265	40010	20	40000	20	110000	1	50000	10
50024	40037	40011	11	40000	10	40000	30	999265	40010	20	40000	20	110000	1	50000	10
50024	40037	40011	11	40000	10	40000	30	999265	40010	20	40000	20	110000	1	50000	10
50024	40037	40011	11	40000	10	40000	30	999265	40010	20	40000	20	110000	1	50000	10
50024	40037	40011	11	40000	10	40000	30	999265	40010	20	40000	20	110000	1	50000	10
50024	40037	40011	11	40000	10	40000	30	999265	40010	20	40000	20	110000	1	50000	10

Test 6: Latency 1->5

Chain cycles: 2

Code:

  movi v0.16b, 0
  tbx v0.16b, { v1.16b, v2.16b, v3.16b }, v4.16b
  add v4.16b, v0.16b, v0.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4
  movi v4.16b, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 6.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
50204	80033	40101	101	40000	100	40000	300	2039248	40100	200	40003	200	110011	1	50000	100
50204	80033	40101	101	40000	100	40000	300	2039248	40100	200	40004	200	110009	1	50000	100
50204	80033	40101	101	40000	100	40000	300	2039248	40100	200	40003	200	110009	1	50000	100
50204	80033	40101	101	40000	100	40000	300	2039248	40100	200	40003	200	110009	1	50000	100
50204	80033	40101	101	40000	100	40000	300	2039248	40100	200	40003	200	110009	1	50000	100
50204	80033	40101	101	40000	100	40000	300	2039248	40100	200	40003	200	110009	1	50000	100
50205	80066	40111	103	40008	102	40034	300	2039248	40100	200	40003	200	110009	1	50000	100
50204	80033	40101	101	40000	100	40000	300	2039248	40100	200	40003	200	110009	1	50000	100
50204	80033	40101	101	40000	100	40000	300	2039248	40100	200	40003	200	110009	1	50000	100
50205	80066	40109	101	40008	100	40034	300	2039248	40100	200	40003	200	110009	1	50000	100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 6.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
50024	80033	40011	11	40000	10	40000	30	2039248	40010	20	40003	20	0	110000	1	0	50000	10
50024	80033	40011	11	40000	10	40000	30	2039248	40010	20	40000	20	0	110000	1	0	50000	10
50024	80033	40011	11	40000	10	40000	30	2039248	40010	20	40000	20	0	110000	1	0	50000	10
50024	80033	40011	11	40000	10	40000	30	2039248	40010	20	40000	20	0	110000	1	0	50000	10
50024	80033	40011	11	40000	10	40000	30	2039248	40010	20	40000	20	0	110000	1	0	50000	10
50024	80033	40011	11	40000	10	40000	30	2039248	40010	20	40000	20	0	110000	1	0	50000	10
50024	80033	40011	11	40000	10	40000	30	2039248	40010	20	40000	20	0	110124	1	0	50000	10
50024	80033	40011	11	40000	10	40000	30	2039248	40010	20	40000	20	0	110000	1	0	50000	10
50024	80033	40011	11	40000	10	40000	30	2039248	40010	20	40000	20	0	110000	1	0	50000	10
50024	80033	40011	11	40000	10	40000	30	2039248	40010	20	40000	20	0	110000	1	0	50000	10

Test 7: throughput

Count: 8

Code:

  movi v0.16b, 0
  tbx v0.16b, { v8.16b, v9.16b, v10.16b }, v11.16b
  movi v1.16b, 0
  tbx v1.16b, { v8.16b, v9.16b, v10.16b }, v11.16b
  movi v2.16b, 0
  tbx v2.16b, { v8.16b, v9.16b, v10.16b }, v11.16b
  movi v3.16b, 0
  tbx v3.16b, { v8.16b, v9.16b, v10.16b }, v11.16b
  movi v4.16b, 0
  tbx v4.16b, { v8.16b, v9.16b, v10.16b }, v11.16b
  movi v5.16b, 0
  tbx v5.16b, { v8.16b, v9.16b, v10.16b }, v11.16b
  movi v6.16b, 0
  tbx v6.16b, { v8.16b, v9.16b, v10.16b }, v11.16b
  movi v7.16b, 0
  tbx v7.16b, { v8.16b, v9.16b, v10.16b }, v11.16b

Initialization

  movi v8.16b, 9
  movi v9.16b, 10
  movi v10.16b, 11
  movi v11.16b, 12

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.5005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
320204	120044	240103	101	240002	100	240009	300	1919454	240110	200	240013	200	720039	1	320000	100
320204	120039	240101	101	240000	100	240008	300	1919758	240110	200	240013	200	720036	1	320000	100
320204	120039	240101	101	240000	100	240008	300	1919894	240108	200	240012	200	720036	1	320000	100
320204	120039	240101	101	240000	100	240008	300	1919894	240108	200	240012	200	720036	1	320000	100
320204	120039	240101	101	240000	100	240008	300	1919894	240108	200	240012	200	720036	1	320000	100
320204	120039	240101	101	240000	100	240008	300	1919894	240108	200	240012	200	720036	1	320000	100
320204	120039	240101	101	240000	100	240008	300	1919894	240108	200	240012	200	720036	1	320000	100
320204	120039	240101	101	240000	100	240008	300	1919894	240108	200	240012	200	720036	1	320000	100
320204	120039	240101	101	240000	100	240008	300	1920120	240162	200	240069	200	720036	1	320000	100
320204	120039	240101	101	240000	100	240008	300	1919894	240108	200	240012	200	720036	1	320000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.5007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
320024	120087	240011	11	240000	10	240008	30	1919309	240074	20	240073	20	0	720036	1	0	320000	10
320024	120061	240011	11	240000	10	240000	30	1919674	240010	20	240000	20	0	720000	1	0	320000	10
320024	120052	240011	11	240000	10	240000	30	1919674	240010	20	240000	20	0	720000	1	0	320000	10
320024	120053	240011	11	240000	10	240000	30	1919674	240010	20	240000	20	0	720000	1	0	320000	10
320024	120053	240011	11	240000	10	240000	30	1919674	240010	20	240000	20	0	720000	1	0	320000	10
320024	120053	240011	11	240000	10	240000	30	1919982	240077	20	240075	20	0	720000	1	0	320000	10
320024	120053	240011	11	240000	10	240000	30	1919674	240010	20	240000	20	0	720000	1	0	320000	10
320024	120053	240011	11	240000	10	240000	30	1919674	240010	20	240000	20	0	720000	1	0	320000	10
320024	120053	240011	11	240000	10	240000	30	1919674	240010	20	240000	20	0	720000	1	0	320000	10
320024	120053	240011	11	240000	10	240000	30	1919674	240010	20	240000	20	0	720000	1	0	320000	10

TBX (three register table, 16B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: Latency 1->4

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: Latency 1->5

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 7: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations