Icestorm: TBX (two register table, 16B) measurements

Code:

  tbx v0.16b, { v1.16b, v2.16b }, v3.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
2004	4033	2001	1	2000	2000	101248	2000	2000	6000	1	2000
2004	4033	2001	1	2000	2000	101248	2000	2000	6000	1	2000
2004	4033	2001	1	2000	2000	101248	2000	2000	6000	1	2000
2004	4033	2001	1	2000	2000	101248	2000	2000	6000	1	2000
2004	4033	2001	1	2000	2000	101248	2000	2000	6000	1	2000
2004	4033	2001	1	2000	2000	101248	2000	2000	6000	1	2000
2004	4033	2001	1	2000	2000	101248	2000	2000	6000	1	2000
2004	4033	2001	1	2000	2000	101248	2000	2000	6000	1	2000
2004	4033	2001	1	2000	2000	101248	2000	2000	6000	1	2000
2004	4033	2001	1	2000	2000	101248	2000	2000	6000	1	2000

Test 2: Latency 1->1

Code:

  tbx v0.16b, { v1.16b, v2.16b }, v3.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
20204	40033	20101	101	20000	100	20000	300	1019248	20100	200	20006	200	60012	1	20000	100
20204	40033	20101	101	20000	100	20000	300	1019248	20100	200	20004	200	60012	1	20000	100
20204	40033	20101	101	20000	100	20000	300	1019248	20100	200	20004	200	60012	1	20000	100
20204	40033	20101	101	20000	100	20000	300	1019248	20100	200	20004	200	60012	1	20000	100
20204	40033	20101	101	20000	100	20000	300	1019248	20100	200	20004	200	60144	1	20000	100
20204	40033	20101	101	20000	100	20000	300	1019248	20100	200	20004	200	60012	1	20000	100
20204	40033	20101	101	20000	100	20000	300	1019248	20100	200	20006	200	60012	1	20000	100
20204	40033	20101	101	20000	100	20000	300	1019580	20134	200	20046	200	60012	1	20000	100
20204	40033	20101	101	20000	100	20000	300	1019248	20100	200	20004	200	60012	1	20000	100
20204	40033	20101	101	20000	100	20000	300	1019248	20100	200	20004	200	60012	1	20000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
20024	40033	20011	11	20000	0	10	20000	30	1019248	20010	20	20006	20	60018	1	20000	10
20024	40033	20011	11	20000	0	10	20000	30	1019248	20010	20	20000	20	60000	1	20000	10
20024	40033	20011	11	20000	0	10	20000	30	1019248	20010	20	20000	20	60000	1	20000	10
20024	40033	20011	11	20000	0	10	20000	30	1019248	20010	20	20000	20	60000	1	20000	10
20024	40033	20011	11	20000	0	10	20000	30	1019248	20010	20	20000	20	60000	1	20000	10
20024	40033	20011	11	20000	0	10	20000	30	1019248	20010	20	20000	20	60000	1	20000	10
20024	40033	20011	11	20000	0	10	20000	30	1019248	20010	20	20000	20	60000	1	20000	10
20024	40033	20011	11	20000	0	10	20000	30	1019248	20010	20	20000	20	60000	1	20000	10
20024	40033	20011	11	20000	0	10	20000	30	1019248	20010	20	20000	20	60000	1	20000	10
20024	40033	20011	11	20000	0	10	20000	30	1019248	20010	20	20000	20	60000	1	20000	10

Test 3: Latency 1->2

Chain cycles: 2

Code:

  movi v0.16b, 0
  tbx v0.16b, { v1.16b, v2.16b }, v3.16b
  add v1.16b, v0.16b, v0.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
40204	60033	30101	101	30000	100	30000	300	1529248	30100	200	30004	200	80011	1	40000	100
40204	60033	30101	101	30000	100	30000	300	1529248	30100	200	30004	200	80008	1	40000	100
40204	60033	30101	101	30000	100	30000	300	1529248	30100	200	30003	200	80008	1	40000	100
40204	60033	30101	101	30000	100	30000	300	1529248	30100	200	30003	200	80008	1	40000	100
40204	60033	30101	101	30000	100	30000	300	1529248	30100	200	30003	200	80008	1	40000	100
40204	60033	30101	101	30000	100	30000	300	1529248	30100	200	30003	200	80008	1	40000	100
40204	60033	30101	101	30000	100	30000	300	1529248	30100	200	30003	200	80118	1	40000	100
40204	60033	30101	101	30000	100	30000	300	1529248	30100	200	30003	200	80008	1	40000	100
40204	60033	30101	101	30000	100	30000	300	1529248	30100	200	30003	200	80008	1	40000	100
40204	60033	30101	101	30000	100	30000	300	1529248	30100	200	30003	200	80008	1	40000	100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
40024	60033	30011	11	30000	10	30000	30	1529248	30010	20	30000	20	80000	1	40000	10
40024	60033	30011	11	30000	10	30000	30	1529248	30010	20	30000	20	80000	1	40000	10
40024	60033	30011	11	30000	10	30000	30	1529248	30010	20	30000	20	80000	1	40000	10
40024	60033	30011	11	30000	10	30000	30	1529248	30010	20	30000	20	80000	1	40000	10
40024	60033	30011	11	30000	10	30000	30	1529248	30010	20	30000	20	80000	1	40000	10
40024	60033	30011	11	30000	10	30000	30	1529248	30010	20	30000	20	80000	1	40000	10
40024	60033	30011	11	30000	10	30000	30	1529248	30010	20	30000	20	80000	1	40000	10
40024	60033	30011	11	30000	10	30000	30	1529248	30010	20	30000	20	80000	1	40000	10
40024	60033	30011	11	30000	10	30000	30	1529248	30010	20	30000	20	80000	1	40000	10
40024	60033	30011	11	30000	10	30000	30	1529248	30010	20	30000	20	80000	1	40000	10

Test 4: Latency 1->3

Chain cycles: 2

Code:

  movi v0.16b, 0
  tbx v0.16b, { v1.16b, v2.16b }, v3.16b
  add v2.16b, v0.16b, v0.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 2.0035

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
40204	40035	30101	101	30000	100	30000	300	1009232	30100	200	30007	200	80019	1	40000	100
40204	40035	30101	101	30000	100	30000	300	1009243	30100	200	30006	200	80016	1	40000	100
40204	40035	30101	101	30000	100	30000	300	1009243	30100	200	30006	200	80016	1	40000	100
40204	40035	30101	101	30000	100	30000	300	1009243	30100	200	30006	200	80016	1	40000	100
40204	40035	30101	101	30000	100	30000	300	1009243	30100	200	30006	200	80016	1	40000	100
40205	40071	30125	101	30024	100	30049	300	1009232	30100	200	30006	200	80016	1	40000	100
40204	40035	30101	101	30000	100	30000	300	1009230	30100	200	30007	200	80016	1	40000	100
40204	40035	30101	101	30000	100	30000	300	1009243	30100	200	30006	200	80016	1	40000	100
40204	40035	30101	101	30000	100	30000	300	1009243	30100	200	30006	200	80016	1	40000	100
40204	40035	30101	101	30000	100	30000	300	1009243	30100	200	30006	200	80016	1	40000	100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 2.0035

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
40024	40035	30011	11	30000	10	30000	30	1009228	30010	20	30000	20	80000	1	40000	10
40024	40035	30011	11	30000	10	30000	30	1009243	30010	20	30000	20	80000	1	40000	10
40024	40035	30011	11	30000	10	30000	30	1009243	30010	20	30000	20	80000	1	40000	10
40024	40035	30011	11	30000	10	30000	30	1009243	30010	20	30000	20	80000	1	40000	10
40024	40035	30011	11	30000	10	30000	30	1009243	30010	20	30000	20	80000	1	40000	10
40024	40035	30011	11	30000	10	30000	30	1009243	30010	20	30000	20	80000	1	40000	10
40024	40035	30011	11	30000	10	30000	30	1009243	30010	20	30000	20	80169	1	40000	10
40024	40035	30011	11	30000	10	30000	30	1009224	30010	20	30006	20	80016	1	40000	10
40024	40035	30011	11	30000	10	30000	30	1009243	30010	20	30000	20	80000	1	40000	10
40024	40035	30011	11	30000	10	30000	30	1010249	30114	20	30111	20	80000	1	40000	10

Test 5: Latency 1->4

Chain cycles: 2

Code:

  movi v0.16b, 0
  tbx v0.16b, { v1.16b, v2.16b }, v3.16b
  add v3.16b, v0.16b, v0.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
40204	60033	30101	101	30000	100	30000	300	1529248	30100	200	30004	200	80008	1	40000	100
40204	60033	30101	101	30000	100	30000	300	1529248	30100	200	30003	200	80008	1	40000	100
40204	60033	30101	101	30000	100	30000	300	1529248	30100	200	30003	200	80008	1	40000	100
40204	60033	30101	101	30000	100	30000	300	1529248	30100	200	30003	200	80120	1	40000	100
40204	60033	30101	101	30000	100	30000	300	1529248	30100	200	30003	200	80008	1	40000	100
40204	60033	30101	101	30000	100	30000	300	1529248	30100	200	30003	200	80008	1	40000	100
40204	60033	30101	101	30000	100	30000	300	1529248	30100	200	30003	200	80008	1	40000	100
40204	60033	30101	101	30000	100	30000	300	1529248	30100	200	30003	200	80008	1	40000	100
40204	60033	30101	101	30000	100	30000	300	1529248	30100	200	30003	200	80008	1	40000	100
40204	60033	30101	101	30000	100	30000	300	1529248	30100	200	30003	200	80008	1	40000	100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
40024	60033	30011	11	30000	10	30000	0	30	0	1529248	30010	20	0	30004	20	80000	1	40000	10
40024	60033	30011	11	30000	10	30000	0	30	0	1529248	30010	20	0	30000	20	80000	1	40000	10
40024	60033	30011	11	30000	10	30000	0	30	0	1529248	30010	20	0	30000	20	80000	1	40000	10
40024	60033	30011	11	30000	10	30000	0	30	0	1529248	30010	20	0	30000	20	80000	1	40000	10
40024	60033	30011	11	30000	10	30000	0	30	0	1529248	30010	20	0	30000	20	80000	1	40000	10
40024	60033	30011	11	30000	10	30000	0	30	0	1529248	30010	20	0	30000	20	80000	1	40000	10
40024	60033	30011	11	30000	10	30000	0	30	0	1529248	30010	20	0	30000	20	80000	1	40000	10
40024	60033	30011	11	30000	10	30000	0	30	0	1529248	30010	20	0	30000	20	80000	1	40000	10
40024	60033	30011	11	30000	10	30000	0	30	0	1529248	30010	20	0	30000	20	80000	1	40000	10
40024	60033	30011	11	30000	10	30000	0	30	0	1529248	30010	20	0	30000	20	80117	1	40000	10

Test 6: throughput

Count: 8

Code:

  movi v0.16b, 0
  tbx v0.16b, { v8.16b, v9.16b }, v10.16b
  movi v1.16b, 0
  tbx v1.16b, { v8.16b, v9.16b }, v10.16b
  movi v2.16b, 0
  tbx v2.16b, { v8.16b, v9.16b }, v10.16b
  movi v3.16b, 0
  tbx v3.16b, { v8.16b, v9.16b }, v10.16b
  movi v4.16b, 0
  tbx v4.16b, { v8.16b, v9.16b }, v10.16b
  movi v5.16b, 0
  tbx v5.16b, { v8.16b, v9.16b }, v10.16b
  movi v6.16b, 0
  tbx v6.16b, { v8.16b, v9.16b }, v10.16b
  movi v7.16b, 0
  tbx v7.16b, { v8.16b, v9.16b }, v10.16b

Initialization

  movi v8.16b, 9
  movi v9.16b, 10
  movi v10.16b, 11

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
240204	80097	160207	201	160006	200	160012	160	15753	7543	800270	160673	579	191	160067	200	0	480039	101	0	240000	100
240204	80036	160207	201	160006	200	160012	0	700	0	800270	160258	200	0	160068	200	0	480051	101	0	240000	100
240205	80072	160241	201	160040	200	160056	0	700	0	800051	160210	200	0	160013	8073	5402	411132	3416	2340	205397	3862
240204	80036	160205	201	160004	200	160010	1858	105194	64832	645530	134268	4414	2171	129118	200	0	480051	101	0	240000	100
240204	80036	160207	201	160006	200	160012	0	700	0	800051	160210	200	0	160013	200	0	480039	101	0	240000	100
240204	80036	160205	201	160004	200	160010	0	700	0	800270	160258	200	0	160067	200	0	480039	101	0	240000	100
240204	80036	160205	201	160004	200	160010	0	700	0	800051	160210	200	0	160013	200	0	480039	101	0	240000	100
240204	80036	160205	201	160004	200	160010	0	700	0	800051	160210	200	0	160013	200	0	480039	101	0	240000	100
240204	80036	160205	201	160004	200	160010	0	700	0	800051	160210	200	0	160013	200	0	480039	101	0	240000	100
240204	80036	160205	201	160004	200	160010	0	700	0	800051	160210	200	0	160013	200	0	480039	101	0	240000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
240024	80407	160015	11	160004	0	10	160010	30	800000	160010	20	160000	20	480000	1	240000	10
240024	80135	160011	11	160000	0	10	160000	30	800000	160010	20	160000	20	480000	1	240000	10
240024	80037	160011	11	160000	0	10	160000	30	800000	160010	20	160000	20	480000	1	240000	10
240024	80044	160011	11	160000	0	10	160000	30	800000	160010	20	160000	20	480000	1	240000	10
240024	80036	160011	11	160000	0	10	160000	30	800000	160010	20	160000	20	480000	1	240000	10
240024	80036	160011	11	160000	0	10	160000	30	800000	160010	20	160000	20	480000	1	240000	10
240024	80036	160011	11	160000	0	10	160000	30	800000	160010	20	160000	20	480000	1	240000	10
240024	80036	160011	11	160000	0	10	160000	30	800000	160010	20	160000	20	480000	1	240000	10
240024	80036	160011	11	160000	0	10	160000	30	800000	160010	20	160000	20	480000	1	240000	10
240024	80036	160011	11	160000	0	10	160000	30	800000	160010	20	160000	20	480000	1	240000	10

TBX (two register table, 16B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: Latency 1->4

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations