Icestorm: TBX (two register table, 8B) measurements

Code:

  tbx v0.8b, { v1.16b, v2.16b }, v3.8b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
2004	4033	2001	1	2000	2000	101248	2000	2000	6000	1	2000
2004	4033	2001	1	2000	2000	101248	2000	2000	6000	1	2000
2004	4033	2001	1	2000	2000	101248	2000	2000	6000	1	2000
2004	4033	2001	1	2000	2000	101248	2000	2000	6000	1	2000
2004	4033	2001	1	2000	2000	101248	2000	2000	6000	1	2000
2004	4033	2001	1	2000	2000	101248	2000	2000	6000	1	2000
2004	4033	2001	1	2000	2000	101248	2000	2000	6000	1	2000
2004	4033	2001	1	2000	2000	101248	2000	2000	6000	1	2000
2004	4033	2001	1	2000	2000	101248	2000	2000	6000	1	2000
2004	4033	2001	1	2000	2000	101248	2000	2000	6000	1	2000

Test 2: Latency 1->1

Code:

  tbx v0.8b, { v1.16b, v2.16b }, v3.8b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
20204	40033	20101	101	20000	100	20000	300	1019248	20100	200	20006	200	60012	1	20000	100
20204	40033	20101	101	20000	100	20000	300	1019248	20100	200	20004	200	60012	1	20000	100
20204	40033	20101	101	20000	100	20000	300	1019248	20100	200	20004	200	60012	1	20000	100
20204	40033	20101	101	20000	100	20000	300	1019248	20100	200	20004	200	60012	1	20000	100
20204	40033	20101	101	20000	100	20000	300	1019248	20100	200	20004	200	60012	1	20000	100
20204	40033	20101	101	20000	100	20000	300	1019248	20100	200	20004	200	60012	1	20000	100
20204	40033	20101	101	20000	100	20000	300	1019248	20100	200	20004	200	60012	1	20000	100
20204	40033	20101	101	20000	100	20000	300	1019248	20100	200	20004	200	60012	1	20000	100
20204	40033	20101	101	20000	100	20000	300	1019248	20100	200	20004	200	60012	1	20000	100
20204	40033	20101	101	20000	100	20000	300	1019248	20100	200	20004	200	60012	1	20000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
20024	40033	20011	11	20000	10	20000	30	1019248	20010	20	20000	20	60000	1	20000	10
20024	40033	20011	11	20000	10	20000	30	1019248	20010	20	20000	20	60000	1	20000	10
20024	40033	20011	11	20000	10	20000	30	1019248	20010	20	20000	20	60000	1	20000	10
20024	40033	20011	11	20000	10	20000	30	1019248	20010	20	20000	20	60144	1	20000	10
20024	40033	20011	11	20000	10	20000	30	1019248	20010	20	20000	20	60000	1	20000	10
20024	40033	20011	11	20000	10	20000	30	1019248	20010	20	20000	20	60000	1	20000	10
20024	40033	20011	11	20000	10	20000	30	1019248	20010	20	20000	20	60000	1	20000	10
20024	40033	20011	11	20000	10	20000	30	1019248	20010	20	20000	20	60000	1	20000	10
20024	40033	20011	11	20000	10	20000	30	1019248	20010	20	20000	20	60000	1	20000	10
20024	40033	20011	11	20000	10	20000	30	1019248	20010	20	20000	20	60000	1	20000	10

Test 3: Latency 1->2

Chain cycles: 2

Code:

  movi v0.16b, 0
  tbx v0.8b, { v1.16b, v2.16b }, v3.8b
  add v1.16b, v0.16b, v0.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
40204	60033	30101	101	30000	100	30000	300	1529248	30100	200	30004	200	80008	1	40000	100
40204	60033	30101	101	30000	100	30000	300	1529580	30134	200	30044	200	80008	1	40000	100
40204	60033	30101	101	30000	100	30000	300	1529248	30100	200	30003	200	80008	1	40000	100
40204	60033	30101	101	30000	100	30000	300	1529248	30100	200	30003	200	80008	1	40000	100
40204	60033	30101	101	30000	100	30000	300	1529248	30100	200	30003	200	80011	1	40000	100
40204	60033	30101	101	30000	100	30000	300	1529248	30100	200	30003	200	80008	1	40000	100
40204	60033	30101	101	30000	100	30000	300	1529248	30100	200	30003	200	80008	1	40000	100
40204	60033	30101	101	30000	100	30000	300	1529248	30100	200	30003	200	80008	1	40000	100
40205	60066	30109	101	30008	100	30034	300	1529248	30100	200	30003	200	80008	1	40000	100
40204	60033	30101	101	30000	100	30000	300	1529248	30100	200	30003	200	80008	1	40000	100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
40024	60033	30011	11	30000	10	30000	30	1529248	30010	20	30004	20	80008	1	40000	10
40024	60033	30011	11	30000	10	30000	30	1529248	30010	20	30000	20	80000	1	40000	10
40024	60033	30011	11	30000	10	30000	30	1529248	30010	20	30000	20	80000	1	40000	10
40024	60033	30011	11	30000	10	30000	30	1529248	30010	20	30000	20	80000	1	40000	10
40024	60033	30011	11	30000	10	30000	30	1529248	30010	20	30000	20	80000	1	40000	10
40024	60033	30011	11	30000	10	30000	30	1529248	30010	20	30000	20	80000	1	40000	10
40024	60033	30011	11	30000	10	30000	30	1529248	30010	20	30000	20	80000	1	40000	10
40024	60033	30011	11	30000	10	30000	30	1529248	30010	20	30000	20	80000	1	40000	10
40024	60033	30011	11	30000	10	30000	30	1529580	30044	20	30045	20	80000	1	40000	10
40024	60033	30011	11	30000	10	30000	30	1529248	30010	20	30000	20	80000	1	40000	10

Test 4: Latency 1->3

Chain cycles: 2

Code:

  movi v0.16b, 0
  tbx v0.8b, { v1.16b, v2.16b }, v3.8b
  add v2.16b, v0.16b, v0.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 2.0035

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
40204	40035	30101	101	30000	100	30000	300	1009225	30100	200	30007	200	80019	1	40000	100
40204	40035	30101	101	30000	100	30000	300	1009243	30100	200	30006	200	80016	1	40000	100
40204	40035	30101	101	30000	100	30000	300	1009243	30100	200	30006	200	80016	1	40000	100
40204	40035	30101	101	30000	100	30000	300	1009243	30100	200	30006	200	80016	1	40000	100
40204	40035	30101	101	30000	100	30000	300	1009491	30150	200	30063	200	80016	1	40000	100
40204	40035	30101	101	30000	100	30000	300	1009243	30100	200	30006	200	80016	1	40000	100
40204	40035	30101	101	30000	100	30000	300	1009243	30100	200	30006	200	80016	1	40000	100
40204	40035	30101	101	30000	100	30000	300	1009243	30100	200	30006	200	80016	1	40000	100
40204	40035	30101	101	30000	100	30000	300	1009243	30100	200	30006	200	80016	1	40000	100
40204	40035	30101	101	30000	100	30000	300	1009243	30100	200	30006	200	80016	1	40000	100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 2.0035

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
40024	40035	30011	11	30000	10	30000	30	1009243	30010	20	30000	20	80000	1	40000	10
40024	40035	30011	11	30000	10	30000	30	1009243	30010	20	30000	20	80000	1	40000	10
40024	40035	30011	11	30000	10	30000	30	1009243	30010	20	30000	20	80000	1	40000	10
40024	40035	30011	11	30000	10	30000	30	1009243	30010	20	30000	20	80000	1	40000	10
40024	40035	30011	11	30000	10	30000	30	1009486	30059	20	30062	20	80000	1	40000	10
40024	40035	30011	11	30000	10	30000	30	1009243	30010	20	30000	20	80000	1	40000	10
40024	40035	30011	11	30000	10	30000	30	1009243	30010	20	30000	20	80000	1	40000	10
40024	40035	30011	11	30000	10	30000	30	1009243	30010	20	30000	20	80000	1	40000	10
40024	40035	30011	11	30000	10	30000	30	1009243	30010	20	30000	20	80000	1	40000	10
40024	40035	30011	11	30000	10	30000	30	1009243	30010	20	30000	20	80000	1	40000	10

Test 5: Latency 1->4

Chain cycles: 2

Code:

  movi v0.16b, 0
  tbx v0.8b, { v1.16b, v2.16b }, v3.8b
  add v3.16b, v0.16b, v0.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3
  movi v3.16b, 4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
40204	60033	30101	101	30000	100	30000	300	1529248	30100	200	30004	200	80011	1	40000	100
40204	60033	30101	101	30000	100	30000	300	1529248	30100	200	30003	200	80008	1	40000	100
40204	60033	30101	101	30000	100	30000	300	1529248	30100	200	30003	200	80008	1	40000	100
40204	60033	30101	101	30000	100	30000	300	1529248	30100	200	30003	200	80008	1	40000	100
40204	60033	30101	101	30000	100	30000	300	1529248	30100	200	30003	200	80008	1	40000	100
40204	60033	30101	101	30000	100	30000	300	1529248	30100	200	30003	200	80008	1	40000	100
40204	60033	30101	101	30000	100	30000	300	1529248	30100	200	30003	200	80008	1	40000	100
40204	60033	30101	101	30000	100	30000	300	1529248	30100	200	30003	200	80008	1	40000	100
40204	60033	30101	101	30000	100	30000	300	1529580	30134	200	30045	200	80008	1	40000	100
40204	60033	30101	101	30000	100	30000	300	1529248	30100	200	30003	200	80008	1	40000	100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 4.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
40024	60033	30011	11	30000	10	30000	30	1529248	30010	20	30004	20	80000	1	40000	10
40024	60033	30011	11	30000	10	30000	30	1529248	30010	20	30000	20	80000	1	40000	10
40024	60033	30011	11	30000	10	30000	30	1529248	30010	20	30000	20	80000	1	40000	10
40024	60033	30011	11	30000	10	30000	30	1529248	30010	20	30000	20	80000	1	40000	10
40024	60033	30011	11	30000	10	30000	30	1529248	30010	20	30000	20	80000	1	40000	10
40024	60033	30011	11	30000	10	30000	30	1529248	30010	20	30000	20	80000	1	40000	10
40024	60033	30011	11	30000	10	30000	30	1529248	30010	20	30000	20	80000	1	40000	10
40024	60033	30011	11	30000	10	30000	30	1529248	30010	20	30000	20	80000	1	40000	10
40024	60033	30011	11	30000	10	30000	30	1529248	30010	20	30000	20	80000	1	40000	10
40024	60033	30011	11	30000	10	30000	30	1529248	30010	20	30000	20	80000	1	40000	10

Test 6: throughput

Count: 8

Code:

  movi v0.16b, 0
  tbx v0.8b, { v8.16b, v9.16b }, v10.8b
  movi v1.16b, 0
  tbx v1.8b, { v8.16b, v9.16b }, v10.8b
  movi v2.16b, 0
  tbx v2.8b, { v8.16b, v9.16b }, v10.8b
  movi v3.16b, 0
  tbx v3.8b, { v8.16b, v9.16b }, v10.8b
  movi v4.16b, 0
  tbx v4.8b, { v8.16b, v9.16b }, v10.8b
  movi v5.16b, 0
  tbx v5.8b, { v8.16b, v9.16b }, v10.8b
  movi v6.16b, 0
  tbx v6.8b, { v8.16b, v9.16b }, v10.8b
  movi v7.16b, 0
  tbx v7.8b, { v8.16b, v9.16b }, v10.8b

Initialization

  movi v8.16b, 9
  movi v9.16b, 10
  movi v10.16b, 11

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
240204	80102	160205	201	160004	200	160010	700	800051	160210	200	160013	200	480039	101	240000	100
240204	80036	160207	201	160006	200	160012	700	800051	160210	200	160013	200	480039	101	240000	100
240204	80036	160207	201	160006	200	160012	700	800051	160210	200	160013	200	480039	101	240000	100
240204	80036	160205	201	160004	200	160010	700	800051	160210	200	160013	200	480039	101	240000	100
240204	80036	160205	201	160004	200	160010	700	800051	160210	200	160013	200	480039	101	240000	100
240204	80036	160205	201	160004	200	160010	700	800051	160210	200	160013	200	480198	101	240000	100
240204	80036	160205	201	160004	200	160010	700	800051	160210	200	160013	200	480039	101	240000	100
240204	80036	160205	201	160004	200	160010	700	800051	160210	200	160013	200	480039	101	240000	100
240204	80036	160205	201	160004	200	160010	700	800051	160210	200	160013	200	480039	101	240000	100
240204	80036	160205	201	160004	200	160010	700	800051	160210	200	160013	200	480039	101	240000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
240024	80453	160015	11	160004	10	160010	30	800000	160010	20	160000	20	0	480000	1	0	240000	10
240024	80058	160011	11	160000	10	160000	30	800000	160010	20	160000	20	0	480000	1	0	240000	10
240024	80036	160011	11	160000	10	160000	30	800000	160010	20	160000	20	0	480192	1	0	240000	10
240024	80036	160011	11	160000	10	160000	30	800000	160010	20	160000	20	0	480000	1	0	240000	10
240025	80074	160049	11	160038	10	160054	30	800000	160010	20	160000	20	0	480000	1	0	240000	10
240024	80036	160011	11	160000	10	160000	30	800000	160010	20	160000	20	0	480000	1	0	240000	10
240024	80036	160011	11	160000	10	160000	30	800000	160010	20	160000	20	0	480000	1	0	240000	10
240024	80037	160011	11	160000	10	160000	30	800000	160010	20	160000	20	0	480000	1	0	240000	10
240024	80036	160011	11	160000	10	160000	30	800000	160010	20	160000	20	0	480000	1	0	240000	10
240024	80036	160011	11	160000	10	160000	30	800000	160010	20	160000	20	0	480000	1	0	240000	10

TBX (two register table, 8B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: Latency 1->4

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations