Icestorm: UABAL2 (vector, 2D) measurements

Code:

  uabal2 v0.2d, v1.4s, v2.4s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000

Test 2: Latency 1->1

Code:

  uabal2 v0.2d, v1.4s, v2.4s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30132	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10004	20	30012	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	67	769247	10051	20	10044	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10

Test 3: Latency 1->2

Code:

  uabal2 v0.2d, v0.4s, v1.4s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10006	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	303	769162	10132	202	10046	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	30033	10021	21	10000	20	10000	0	70	0	768905	10020	20	0	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	0	70	0	768905	10020	20	0	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	0	70	0	768905	10020	20	0	10000	20	30000	11	10000	10
10025	30066	10027	21	10006	20	10031	0	70	0	768905	10020	20	0	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	0	70	0	768905	10020	20	0	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	0	70	0	768905	10020	20	0	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	2426	38023	23608	770677	15357	4172	2909	10071	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	0	70	0	768905	10020	20	0	10000	22	30114	12	10000	10
10024	30033	10021	21	10000	20	10000	0	70	0	768905	10020	20	0	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	0	70	0	768905	10020	20	0	10000	20	30000	11	10000	10

Test 4: Latency 1->3

Code:

  uabal2 v0.2d, v1.4s, v0.4s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	30033	10101	101	10000	100	10000	0	300	0	768905	10100	200	0	10004	200	30018	1	10000	100
10204	30033	10101	101	10000	100	10000	1543	71561	18334	772694	13989	3294	1886	10091	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	0	300	0	768905	10100	200	0	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	0	300	0	768905	10100	200	0	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	0	300	0	768905	10100	200	0	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	0	300	0	768905	10100	200	0	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	0	300	0	768905	10100	200	0	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	0	300	0	768905	10100	200	0	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	0	300	0	768905	10100	200	0	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	0	300	0	768905	10100	200	0	10004	200	30012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  uabal2 v0.2d, v8.4s, v9.4s
  movi v1.16b, 0
  uabal2 v1.2d, v8.4s, v9.4s
  movi v2.16b, 0
  uabal2 v2.2d, v8.4s, v9.4s
  movi v3.16b, 0
  uabal2 v3.2d, v8.4s, v9.4s
  movi v4.16b, 0
  uabal2 v4.2d, v8.4s, v9.4s
  movi v5.16b, 0
  uabal2 v5.2d, v8.4s, v9.4s
  movi v6.16b, 0
  uabal2 v6.2d, v8.4s, v9.4s
  movi v7.16b, 0
  uabal2 v7.2d, v8.4s, v9.4s

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160205	40553	80145	101	80044	100	80048	300	320056	80113	200	80013	200	240039	1	160000	100
160204	40124	80110	101	80009	100	80013	300	320056	80113	200	80013	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240144	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5054

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160024	43852	80019	11	80008	10	80012	30	320056	80023	20	80013	20	240000	1	160000	10
160024	41235	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40454	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40402	80011	11	80000	10	80000	30	320192	80057	20	80047	20	240000	1	160000	10
160024	43900	80020	11	80009	10	80013	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40477	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40393	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40409	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40428	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40429	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10

Test 6: throughput

Count: 16

Code:

  uabal2 v0.2d, v16.4s, v17.4s
  uabal2 v1.2d, v16.4s, v17.4s
  uabal2 v2.2d, v16.4s, v17.4s
  uabal2 v3.2d, v16.4s, v17.4s
  uabal2 v4.2d, v16.4s, v17.4s
  uabal2 v5.2d, v16.4s, v17.4s
  uabal2 v6.2d, v16.4s, v17.4s
  uabal2 v7.2d, v16.4s, v17.4s
  uabal2 v8.2d, v16.4s, v17.4s
  uabal2 v9.2d, v16.4s, v17.4s
  uabal2 v10.2d, v16.4s, v17.4s
  uabal2 v11.2d, v16.4s, v17.4s
  uabal2 v12.2d, v16.4s, v17.4s
  uabal2 v13.2d, v16.4s, v17.4s
  uabal2 v14.2d, v16.4s, v17.4s
  uabal2 v15.2d, v16.4s, v17.4s

Initialization

  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160204	80054	160108	101	160007	100	160011	0	300	0	640044	160110	200	0	160014	200	0	480042	1	0	160000	100
160204	80035	160107	101	160006	100	160010	0	300	0	640036	160108	200	0	160012	200	0	480036	1	0	160000	100
160204	80035	160105	101	160004	100	160008	0	300	0	640036	160108	200	0	160012	200	0	480036	1	0	160000	100
160204	80035	160105	101	160004	100	160008	0	300	0	640036	160108	200	0	160012	200	0	480192	1	0	160000	100
160204	80035	160107	101	160006	100	160010	0	300	0	640036	160108	200	0	160012	200	0	480036	1	0	160000	100
160204	80035	160105	101	160004	100	160008	0	300	0	640036	160108	200	0	160012	200	0	480036	1	0	160000	100
160204	80035	160105	101	160004	100	160008	0	300	0	640036	160108	200	0	160012	200	0	480036	1	0	160000	100
160204	80035	160105	101	160004	100	160008	0	300	0	640208	160154	200	0	160062	200	0	480036	1	0	160000	100
160204	80035	160105	101	160004	100	160008	0	300	0	640036	160108	200	0	160012	200	0	480036	1	0	160000	100
160204	80035	160105	101	160004	100	160008	0	300	0	640036	160108	200	0	160012	200	0	480036	1	0	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160024	80135	160015	11	160004	10	160008	30	640044	160020	20	160014	20	480000	1	160000	10
160024	80036	160011	11	160000	10	160000	30	640000	160010	20	160000	20	480000	1	160000	10
160024	80036	160011	11	160000	10	160000	30	640000	160010	20	160000	20	480000	1	160000	10
160024	80036	160011	11	160000	10	160000	30	640216	160066	20	160063	20	480000	1	160000	10
160024	80036	160011	11	160000	10	160000	30	640000	160010	20	160000	20	480000	1	160000	10
160024	80035	160011	11	160000	10	160000	30	640000	160010	20	160000	20	480195	1	160000	10
160024	80036	160011	11	160000	10	160000	30	640000	160010	20	160000	20	480000	1	160000	10
160024	80036	160011	11	160000	10	160000	30	640000	160010	20	160000	20	480000	1	160000	10
160025	80078	160054	11	160043	10	160055	30	640000	160010	20	160000	20	480000	1	160000	10
160024	80036	160011	11	160000	10	160000	30	640000	160010	20	160000	20	480189	1	160000	10

UABAL2 (vector, 2D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations