Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

UABAL2 (vector, 2D)

Test 1: uops

Code:

  uabal2 v0.2d, v1.4s, v2.4s
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000

Test 2: Latency 1->1

Code:

  uabal2 v0.2d, v1.4s, v2.4s
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030132110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024300331002121100002010000707689051002020100042030012111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000677692471005120100442030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010

Test 3: Latency 1->2

Code:

  uabal2 v0.2d, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020430033101011011000010010000300768905101002001000620030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000303769162101322021004620030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024300331002121100002010000070076890510020200100002030000111000010
10024300331002121100002010000070076890510020200100002030000111000010
10024300331002121100002010000070076890510020200100002030000111000010
10025300661002721100062010031070076890510020200100002030000111000010
10024300331002121100002010000070076890510020200100002030000111000010
10024300331002121100002010000070076890510020200100002030000111000010
10024300331002121100002010000242638023236087706771535741722909100712030000111000010
10024300331002121100002010000070076890510020200100002230114121000010
10024300331002121100002010000070076890510020200100002030000111000010
10024300331002121100002010000070076890510020200100002030000111000010

Test 4: Latency 1->3

Code:

  uabal2 v0.2d, v1.4s, v0.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020430033101011011000010010000030007689051010020001000420030018110000100
10204300331010110110000100100001543715611833477269413989329418861009120030012110000100
1020430033101011011000010010000030007689051010020001000420030012110000100
1020430033101011011000010010000030007689051010020001000420030012110000100
1020430033101011011000010010000030007689051010020001000420030012110000100
1020430033101011011000010010000030007689051010020001000420030012110000100
1020430033101011011000010010000030007689051010020001000420030012110000100
1020430033101011011000010010000030007689051010020001000420030012110000100
1020430033101011011000010010000030007689051010020001000420030012110000100
1020430033101011011000010010000030007689051010020001000420030012110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  uabal2 v0.2d, v8.4s, v9.4s
  movi v1.16b, 0
  uabal2 v1.2d, v8.4s, v9.4s
  movi v2.16b, 0
  uabal2 v2.2d, v8.4s, v9.4s
  movi v3.16b, 0
  uabal2 v3.2d, v8.4s, v9.4s
  movi v4.16b, 0
  uabal2 v4.2d, v8.4s, v9.4s
  movi v5.16b, 0
  uabal2 v5.2d, v8.4s, v9.4s
  movi v6.16b, 0
  uabal2 v6.2d, v8.4s, v9.4s
  movi v7.16b, 0
  uabal2 v7.2d, v8.4s, v9.4s
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1602054055380145101800441008004830032005680113200800132002400391160000100
1602044012480110101800091008001330032005680113200800132002400361160000100
1602044008680109101800081008001230032005280112200800122002401441160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5054

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1600244385280019118000810800123032005680023208001320240000116000010
1600244123580011118000010800003032000080010208000020240000116000010
1600244045480011118000010800003032000080010208000020240000116000010
1600244040280011118000010800003032019280057208004720240000116000010
1600244390080020118000910800133032000080010208000020240000116000010
1600244047780011118000010800003032000080010208000020240000116000010
1600244039380011118000010800003032000080010208000020240000116000010
1600244040980011118000010800003032000080010208000020240000116000010
1600244042880011118000010800003032000080010208000020240000116000010
1600244042980011118000010800003032000080010208000020240000116000010

Test 6: throughput

Count: 16

Code:

  uabal2 v0.2d, v16.4s, v17.4s
  uabal2 v1.2d, v16.4s, v17.4s
  uabal2 v2.2d, v16.4s, v17.4s
  uabal2 v3.2d, v16.4s, v17.4s
  uabal2 v4.2d, v16.4s, v17.4s
  uabal2 v5.2d, v16.4s, v17.4s
  uabal2 v6.2d, v16.4s, v17.4s
  uabal2 v7.2d, v16.4s, v17.4s
  uabal2 v8.2d, v16.4s, v17.4s
  uabal2 v9.2d, v16.4s, v17.4s
  uabal2 v10.2d, v16.4s, v17.4s
  uabal2 v11.2d, v16.4s, v17.4s
  uabal2 v12.2d, v16.4s, v17.4s
  uabal2 v13.2d, v16.4s, v17.4s
  uabal2 v14.2d, v16.4s, v17.4s
  uabal2 v15.2d, v16.4s, v17.4s
  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
16020480054160108101160007100160011030006400441601102000160014200048004210160000100
16020480035160107101160006100160010030006400361601082000160012200048003610160000100
16020480035160105101160004100160008030006400361601082000160012200048003610160000100
16020480035160105101160004100160008030006400361601082000160012200048019210160000100
16020480035160107101160006100160010030006400361601082000160012200048003610160000100
16020480035160105101160004100160008030006400361601082000160012200048003610160000100
16020480035160105101160004100160008030006400361601082000160012200048003610160000100
16020480035160105101160004100160008030006402081601542000160062200048003610160000100
16020480035160105101160004100160008030006400361601082000160012200048003610160000100
16020480035160105101160004100160008030006400361601082000160012200048003610160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
160024801351600151116000410160008306400441600202016001420480000116000010
160024800361600111116000010160000306400001600102016000020480000116000010
160024800361600111116000010160000306400001600102016000020480000116000010
160024800361600111116000010160000306402161600662016006320480000116000010
160024800361600111116000010160000306400001600102016000020480000116000010
160024800351600111116000010160000306400001600102016000020480195116000010
160024800361600111116000010160000306400001600102016000020480000116000010
160024800361600111116000010160000306400001600102016000020480000116000010
160025800781600541116004310160055306400001600102016000020480000116000010
160024800361600111116000010160000306400001600102016000020480189116000010