Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

UABAL2 (vector, 8H)

Test 1: uops

Code:

  uabal2 v0.8h, v1.16b, v2.16b
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000

Test 2: Latency 1->1

Code:

  uabal2 v0.8h, v1.16b, v2.16b
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020430033101011011000010010000030007689051010020001000420430246310000100
1020430033101011011000010010000030007689051010020001000420030012110000100
1020430135101171011001610010066030007689051010020001000420030012110000100
1020430033101011011000010010000030007689051010020001000420030012110000100
1020430033101011011000010010000030007689051010020001000420030012110000100
10204300331010110110000100100005256146581612562382551198260471181659961161920030012110000100
1020430033101011011000010010000030007689051010020001000420030012110000100
1020430033101011011000010010000030007689051010020001000420030012110000100
1020430033101011011000010010000030007689051010020001000420030012110000100
1020430033101011011000010010000030007689051010020001000420030012110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024300331002121100002010000707689051002020100042030012111000010
10024300331002121100002010000707689051002020100002030018111000010
10024300331002121100002010000707689051002020100002030132111000010
10024300331002121100002010000707689051002020100002030000111000010
10025300661002721100062010031687705431011920101172030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100042030012111000010

Test 3: Latency 1->2

Code:

  uabal2 v0.8h, v0.16b, v1.16b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020430033101011011000010010000307769247101332021004220030018110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024300331002121100002010000707689051002020100062030012111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002230132121000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010

Test 4: Latency 1->3

Code:

  uabal2 v0.8h, v1.16b, v0.16b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020430033101011011000010010000300768905101002001000620030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420230138210000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024300331002121100002010000707689051002020100062030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  uabal2 v0.8h, v8.16b, v9.16b
  movi v1.16b, 0
  uabal2 v1.8h, v8.16b, v9.16b
  movi v2.16b, 0
  uabal2 v2.8h, v8.16b, v9.16b
  movi v3.16b, 0
  uabal2 v3.8h, v8.16b, v9.16b
  movi v4.16b, 0
  uabal2 v4.8h, v8.16b, v9.16b
  movi v5.16b, 0
  uabal2 v5.8h, v8.16b, v9.16b
  movi v6.16b, 0
  uabal2 v6.8h, v8.16b, v9.16b
  movi v7.16b, 0
  uabal2 v7.8h, v8.16b, v9.16b
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1602054053980145101800441008004830032005680113200800132002400391160000100
1602044010880110101800091008001330032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5054

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1600244369980020118000910800133032005680023208001320240000116000010
1600244136380011118000010800003032000080010208000020240000116000010
1600244040380011118000010800003032000080010208000020240000116000010
1600244042380011118000010800003032000080010208000020240000116000010
1600244042080011118000010800003032000080010208000020240000116000010
1600244040980011118000010800003032000080010208000020240000116000010
1600244044780011118000010800003032000080010208000020240000116000010
1600244041180011118000010800003032000080010208000020240000116000010
1600254053680055118004410800483032000080010208000020240000116000010
1600244045580011118000010800003032000080010208000020240000116000010

Test 6: throughput

Count: 16

Code:

  uabal2 v0.8h, v16.16b, v17.16b
  uabal2 v1.8h, v16.16b, v17.16b
  uabal2 v2.8h, v16.16b, v17.16b
  uabal2 v3.8h, v16.16b, v17.16b
  uabal2 v4.8h, v16.16b, v17.16b
  uabal2 v5.8h, v16.16b, v17.16b
  uabal2 v6.8h, v16.16b, v17.16b
  uabal2 v7.8h, v16.16b, v17.16b
  uabal2 v8.8h, v16.16b, v17.16b
  uabal2 v9.8h, v16.16b, v17.16b
  uabal2 v10.8h, v16.16b, v17.16b
  uabal2 v11.8h, v16.16b, v17.16b
  uabal2 v12.8h, v16.16b, v17.16b
  uabal2 v13.8h, v16.16b, v17.16b
  uabal2 v14.8h, v16.16b, v17.16b
  uabal2 v15.8h, v16.16b, v17.16b
  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
160204800521601071011600061001600103006400441601102001600142004800421160000100
160204800351601071011600061001600103006400361601082001600122004800361160000100
160204800351601051011600041001600083006400361601082001600122004800361160000100
160204800351601051011600041001600083006400361601082001600122004800361160000100
160204800351601051011600041001600083006400361601082001600122004800361160000100
160204800351601051011600041001600083006400361601082001600122004800361160000100
160204800351601051011600041001600083006400361601082001600122004800361160000100
160204800351601051011600041001600083006400361601082001600122004800361160000100
160204800351601051011600041001600083006400361601082001600122004800361160000100
160204800351601051011600041001600083006400361601082001600122004800361160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
160024801051600151116000410160008306400001600102016000020480000116000010
160024800521600111116000010160000306400001600102016000020480000116000010
160024800351600111116000010160000306400001600102016000020480000116000010
160024800351600111116000010160000306400001600102016000020480000116000010
160024800351600111116000010160000306400001600102016000020480000116000010
160024800401600111116000010160000306400001600102016000020480000116000010
160024800361600111116000010160000306400001600102016000020480336116000010
160024800361600111116000010160000306400001600102016000020480000116000010
160024800351600111116000010160000306400001600102016000020480000116000010
160024800351600111116000010160000306400001600102016000020480000116000010