Icestorm: UABA (vector, 16B) measurements

Code:

  uaba v0.16b, v1.16b, v2.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000

Test 2: Latency 1->1

Code:

  uaba v0.16b, v1.16b, v2.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	0	30012	1	0	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	0	30012	1	0	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	0	30012	1	0	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	0	30012	1	0	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	0	30012	1	0	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	0	30132	1	0	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	0	30012	1	0	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	0	30012	1	0	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	0	30012	1	0	10000	100
10204	30033	10101	101	10000	100	10000	307	769247	10133	202	10046	200	0	30012	1	0	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10004	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30132	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10

Test 3: Latency 1->2

Code:

  uaba v0.16b, v0.16b, v1.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	30033	10101	101	10000	0	100	10000	300	768905	10100	200	10006	200	30018	1	10000	100
10204	30033	10101	101	10000	0	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	0	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	0	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	0	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	0	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	0	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	0	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	0	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	0	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	30033	10021	21	10000	20	10000	0	70	0	768905	10020	20	0	10004	20	30018	11	10000	10
10024	30033	10021	21	10000	20	10000	0	70	0	768905	10020	20	0	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	0	70	0	768905	10020	20	0	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	0	70	0	768905	10020	20	0	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	0	70	0	768905	10020	20	0	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	0	70	0	768905	10020	20	0	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	0	70	0	768905	10020	20	0	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	0	70	0	768905	10020	20	0	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	0	70	0	768905	10020	20	0	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	0	70	0	768905	10020	20	0	10000	20	30000	11	10000	10

Test 4: Latency 1->3

Code:

  uaba v0.16b, v1.16b, v0.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	30033	10101	101	10000	100	10000	307	771089	10234	202	10164	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10006	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	769247	10051	20	10044	20	30018	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  uaba v0.16b, v8.16b, v9.16b
  movi v1.16b, 0
  uaba v1.16b, v8.16b, v9.16b
  movi v2.16b, 0
  uaba v2.16b, v8.16b, v9.16b
  movi v3.16b, 0
  uaba v3.16b, v8.16b, v9.16b
  movi v4.16b, 0
  uaba v4.16b, v8.16b, v9.16b
  movi v5.16b, 0
  uaba v5.16b, v8.16b, v9.16b
  movi v6.16b, 0
  uaba v6.16b, v8.16b, v9.16b
  movi v7.16b, 0
  uaba v7.16b, v8.16b, v9.16b

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160204	40542	80109	101	80008	100	80012	300	320056	80113	200	80013	200	240039	1	160000	100
160204	40105	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5053

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160024	43864	80019	11	80008	10	80012	30	320000	80010	20	80000	20	240000	1	160000	10
160024	41248	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40373	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40418	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40409	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40409	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40402	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40422	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40414	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40450	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10

Test 6: throughput

Count: 16

Code:

  uaba v0.16b, v16.16b, v17.16b
  uaba v1.16b, v16.16b, v17.16b
  uaba v2.16b, v16.16b, v17.16b
  uaba v3.16b, v16.16b, v17.16b
  uaba v4.16b, v16.16b, v17.16b
  uaba v5.16b, v16.16b, v17.16b
  uaba v6.16b, v16.16b, v17.16b
  uaba v7.16b, v16.16b, v17.16b
  uaba v8.16b, v16.16b, v17.16b
  uaba v9.16b, v16.16b, v17.16b
  uaba v10.16b, v16.16b, v17.16b
  uaba v11.16b, v16.16b, v17.16b
  uaba v12.16b, v16.16b, v17.16b
  uaba v13.16b, v16.16b, v17.16b
  uaba v14.16b, v16.16b, v17.16b
  uaba v15.16b, v16.16b, v17.16b

Initialization

  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160204	80053	160107	101	160006	100	160010	300	640044	160110	200	160014	200	0	480042	1	0	160000	100
160205	80071	160145	101	160044	100	160056	300	640036	160108	200	160012	200	0	480036	1	0	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	0	480036	1	0	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	0	480036	1	0	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	0	480036	1	0	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	0	480036	1	0	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	0	480036	1	0	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	0	480036	1	0	160000	100
160204	80038	160107	101	160006	100	160010	300	640044	160110	200	160014	200	0	480042	1	0	160000	100
160204	80045	160107	101	160006	100	160010	300	640036	160108	200	160012	200	0	480036	1	0	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160024	80087	160015	11	160004	10	160008	30	640216	160066	20	160063	20	480042	1	160000	10
160024	80061	160011	11	160000	10	160000	30	640216	160066	20	160062	20	480000	1	160000	10
160024	80035	160011	11	160000	10	160000	30	640000	160010	20	160000	20	480000	1	160000	10
160024	80042	160011	11	160000	10	160000	30	640000	160010	20	160000	20	480000	1	160000	10
160024	80035	160011	11	160000	10	160000	30	640000	160010	20	160000	20	480000	1	160000	10
160024	80035	160011	11	160000	10	160000	30	640000	160010	20	160000	20	480000	1	160000	10
160024	80035	160011	11	160000	10	160000	30	640000	160010	20	160000	20	480000	1	160000	10
160024	80035	160011	11	160000	10	160000	30	640204	160063	20	160062	20	480000	1	160000	10
160024	80035	160011	11	160000	10	160000	30	640000	160010	20	160000	20	480000	1	160000	10
160024	80035	160011	11	160000	10	160000	30	640000	160010	20	160000	20	480000	1	160000	10

UABA (vector, 16B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations