Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

UADALP (vector, 1D)

Test 1: uops

Code:

  uadalp v0.1d, v1.2s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000

Test 2: Latency 1->1

Code:

  uadalp v0.1d, v1.2s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020430033101011011000010010000300768905101002001000620020012110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000620020012110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024300331002121100002010000707689051002020100042020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020088111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010

Test 3: Latency 1->2

Code:

  uadalp v0.1d, v0.2s
  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10025300661002721100062010031707689051002020100042020008111000010
10024300331002121100002010000707689051002020100002020096111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002220084121000010
10024300331002121100002010000707689051002020100002020008111000010
10024301341003721100162010066707689051002020100002020082111000010
10025301161003521100142010064707689051002020100002020000111000010
10024301351003721100162010066707689051002020100002020000111000010

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  uadalp v0.1d, v8.2s
  movi v1.16b, 0
  uadalp v1.1d, v8.2s
  movi v2.16b, 0
  uadalp v2.1d, v8.2s
  movi v3.16b, 0
  uadalp v3.1d, v8.2s
  movi v4.16b, 0
  uadalp v4.1d, v8.2s
  movi v5.16b, 0
  uadalp v5.1d, v8.2s
  movi v6.16b, 0
  uadalp v6.1d, v8.2s
  movi v7.16b, 0
  uadalp v7.1d, v8.2s
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1602044046580110101800091008001330032005280112200800122001600241160000100
1602044011080110101800091008001330032020480150200800502001600241160000100
1602044010180110101800091008001330032005280112200800122001600241160000100
1602044008680109101800081008001230032005680113200800132001600241160000100
1602044008680109101800081008001230032005280112200800122001600241160000100
1602044008680109101800081008001230032005280112200800122001600961160000100
1602044009680110101800091008001330032005280112200800122001600241160000100
1602044008680109101800081008001230032005280112200800122001600241160000100
1602044008680109101800081008001230032005280112200800122001600241160000100
1602044008680109101800081008001230032005280112200800122001600241160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5054

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1600244394180019118000810800120300320196800582008004820160026116000010
1600244137380011118000010800000300320000800102008000020160000116000010
1600244043880011118000010800000300320000800102008000020160000116000010
1600244039980011118000010800000300320000800102008000020160000116000010
1600244043580011118000010800000300320000800102008000020160000116000010
1600244044680011118000010800000300320000800102008000020160000116000010
1600244173280011118000010800000300320000800102008000020160000116000010
1600244046980011118000010800000300320000800102008000020160000116000010
1600244041680011118000010800000300320000800102008000020160000116000010
1600244043580011118000010800000300320000800102008000020160000116000010

Test 5: throughput

Count: 16

Code:

  uadalp v0.1d, v16.2s
  uadalp v1.1d, v16.2s
  uadalp v2.1d, v16.2s
  uadalp v3.1d, v16.2s
  uadalp v4.1d, v16.2s
  uadalp v5.1d, v16.2s
  uadalp v6.1d, v16.2s
  uadalp v7.1d, v16.2s
  uadalp v8.1d, v16.2s
  uadalp v9.1d, v16.2s
  uadalp v10.1d, v16.2s
  uadalp v11.1d, v16.2s
  uadalp v12.1d, v16.2s
  uadalp v13.1d, v16.2s
  uadalp v14.1d, v16.2s
  uadalp v15.1d, v16.2s
  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
160204800741601051011600041001600080300064003616010820001600122003200241160000100
160204800351601071011600061001600100300064004416011020001600142003200241160000100
160204800351601051011600041001600080300064003616010820001600122003200241160000100
160204800351601051011600041001600080300064003616010820001600122003200241160000100
160204800351601051011600041001600080300064003616010820001600122003200281160000100
160205800701601411011600401001600520300064003616010820001600122003200241160000100
160204800351601051011600041001600080300064003616010820001600122003200241160000100
160204800351601051011600041001600080300064003616010820001600122003200241160000100
160204800351601051011600041001600080300064003616010820001600122003200241160000100
160204800351601051011600041001600080300064003616010820001600122003200241160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
160024804581600151116000410160008306400001600102016000020320000116000010
160024800571600111116000010160000306400001600102016000020320000116000010
160024800351600111116000010160000306400001600102016000020320000116000010
160024800351600111116000010160000306400001600102016000020320000116000010
160024800351600111116000010160000306400001600102016000020320000116000010
160024800351600111116000010160000306400001600102016000020320124116000010
160024800351600111116000010160000306400001600102016000020320000116000010
160024800351600111116000010160000306400001600102016000020320000116000010
160024800351600111116000010160000306400001600102016000020320000116000010
160024800351600111116000010160000306400001600102016000020320000116000010