Icestorm: UADALP (vector, 4H) measurements

Code:

  uadalp v0.4h, v1.8b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000

Test 2: Latency 1->1

Code:

  uadalp v0.4h, v1.8b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10006	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10006	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10205	30066	10109	103	10006	102	10031	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10006	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10

Test 3: Latency 1->2

Code:

  uadalp v0.4h, v0.8b

Initialization

  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10006	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20088	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	30033	10021	21	10000	20	10000	1401	70772	19324	773532	13562	2798	1720	10082	20	20008	11	10000	10
10024	30033	10021	21	10000	20	10000	0	70	0	768905	10020	20	0	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	0	70	0	768905	10020	20	0	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	0	70	0	768905	10020	20	0	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	0	70	0	768905	10020	20	0	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	0	70	0	768905	10020	20	0	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	0	70	0	768905	10020	20	0	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	0	70	0	768905	10020	20	0	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	0	70	0	768905	10020	20	0	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	0	70	0	768905	10020	20	0	10000	20	20000	11	10000	10

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  uadalp v0.4h, v8.8b
  movi v1.16b, 0
  uadalp v1.4h, v8.8b
  movi v2.16b, 0
  uadalp v2.4h, v8.8b
  movi v3.16b, 0
  uadalp v3.4h, v8.8b
  movi v4.16b, 0
  uadalp v4.4h, v8.8b
  movi v5.16b, 0
  uadalp v5.4h, v8.8b
  movi v6.16b, 0
  uadalp v6.4h, v8.8b
  movi v7.16b, 0
  uadalp v7.4h, v8.8b

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160204	40518	80109	101	80008	100	80012	300	320052	80112	200	80012	200	0	160024	1	0	160000	100
160204	40108	80110	101	80009	100	80013	300	320052	80112	200	80012	200	0	160024	1	0	160000	100
160204	40086	80109	101	80008	100	80012	300	320056	80113	200	80013	200	0	160024	1	0	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	0	160024	1	0	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	0	160024	1	0	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	0	160024	1	0	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	0	160100	1	0	160000	100
160204	40086	80109	101	80008	100	80012	300	320056	80113	200	80013	200	0	160096	1	0	160000	100
160204	40098	80110	101	80009	100	80013	300	320052	80112	200	80012	200	0	160026	1	0	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	0	160024	1	0	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5053

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160024	43716	80019	11	80008	10	80012	30	320056	80023	20	80013	20	160000	1	160000	10
160024	41264	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160025	40922	80054	11	80043	10	80047	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40459	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40414	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40427	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40388	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40416	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40416	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40427	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10

Test 5: throughput

Count: 16

Code:

  uadalp v0.4h, v16.8b
  uadalp v1.4h, v16.8b
  uadalp v2.4h, v16.8b
  uadalp v3.4h, v16.8b
  uadalp v4.4h, v16.8b
  uadalp v5.4h, v16.8b
  uadalp v6.4h, v16.8b
  uadalp v7.4h, v16.8b
  uadalp v8.4h, v16.8b
  uadalp v9.4h, v16.8b
  uadalp v10.4h, v16.8b
  uadalp v11.4h, v16.8b
  uadalp v12.4h, v16.8b
  uadalp v13.4h, v16.8b
  uadalp v14.4h, v16.8b
  uadalp v15.4h, v16.8b

Initialization

  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160204	80076	160105	101	160004	100	160008	300	640036	160108	200	160012	200	0	320024	1	0	160000	100
160204	80035	160107	101	160006	100	160010	300	640036	160108	200	160012	200	0	320024	1	0	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	0	320024	1	0	160000	100
160204	80035	160107	101	160006	100	160010	300	640044	160110	200	160014	200	0	320024	1	0	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	0	320124	1	0	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	0	320024	1	0	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	0	320024	1	0	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	0	320024	1	0	160000	100
160205	80070	160143	101	160042	100	160054	300	640204	160153	200	160061	200	0	320028	1	0	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	0	320024	1	0	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160024	80119	160015	11	160004	10	160008	30	640000	160010	20	160000	20	320000	1	160000	10
160024	80051	160011	11	160000	10	160000	30	640000	160010	20	160000	20	320000	1	160000	10
160024	80035	160011	11	160000	10	160000	30	640000	160010	20	160000	20	320000	1	160000	10
160024	80035	160011	11	160000	10	160000	30	640000	160010	20	160000	20	320000	1	160000	10
160024	80035	160011	11	160000	10	160000	30	640000	160010	20	160000	20	320000	1	160000	10
160024	80035	160011	11	160000	10	160000	30	640200	160062	20	160062	20	320000	1	160000	10
160024	80035	160011	11	160000	10	160000	30	640000	160010	20	160000	20	320000	1	160000	10
160024	80035	160011	11	160000	10	160000	30	640000	160010	20	160000	20	320000	1	160000	10
160025	80070	160051	11	160040	10	160052	30	640036	160018	20	160012	20	320000	1	160000	10
160024	80041	160011	11	160000	10	160000	30	640000	160010	20	160000	20	320000	1	160000	10

UADALP (vector, 4H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations