Icestorm: UCVTF (scalar, fixed-point, D from W) measurements

Code:

  ucvtf d0, w0, #3

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)
2004	631	2001	1	1000	1000	1000	1000	3000	8000	2000	1000	1000	1000	1000	1	1000	1000
2004	540	2001	1	1000	1000	1000	1000	3000	8000	2000	1000	1000	1000	1000	1	1000	1000
2004	537	2001	1	1000	1000	1000	1000	3000	8000	2000	1000	1000	1000	1000	1	1000	1000
2004	537	2001	1	1000	1000	1000	1000	3000	8000	2000	1000	1000	1000	1000	1	1000	1000
2004	537	2001	1	1000	1000	1000	1000	3000	8000	2000	1000	1000	1000	1000	1	1000	1000
2004	537	2001	1	1000	1000	1000	1000	3000	8000	2000	1000	1000	1000	1000	1	1000	1000
2004	537	2001	1	1000	1000	1000	1000	3000	8000	2000	1000	1000	1000	1000	1	1000	1000
2004	537	2001	1	1000	1000	1000	1000	3000	8000	2000	1000	1000	1000	1000	1	1000	1000
2004	537	2001	1	1000	1000	1000	1000	3000	8000	2000	1000	1000	1000	1000	1	1000	1000
2004	537	2001	1	1000	1000	1000	1000	3000	8000	2000	1000	1000	1000	1000	1	1000	1000

Test 2: Latency 1->2 roundtrip

Code:

  ucvtf d0, w0, #3
  fmov x0, d0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 10.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
30204	100030	40101	10101	20000	10000	100	20000	10001	300	1546176	2578264	30101	200	10002	20004	200	10002	20004	10001	10000	10000	10100
30204	100030	40101	10101	20000	10000	100	20000	10000	300	1546174	2578264	30100	200	10002	20002	200	10002	20002	10001	10000	10000	10100
30204	100030	40101	10101	20000	10000	100	20000	10000	300	1546174	2578264	30100	200	10002	20002	200	10002	20002	10001	10000	10000	10100
30204	100030	40101	10101	20000	10000	100	20000	10017	300	1546384	2578617	30146	200	10021	20039	200	10002	20002	10001	10000	10000	10100
30204	100030	40101	10101	20000	10000	100	20000	10000	300	1546174	2578264	30100	200	10002	20002	200	10002	20002	10001	10000	10000	10100
30204	100030	40101	10101	20000	10000	100	20000	10000	300	1546174	2578264	30100	200	10002	20002	200	10002	20002	10001	10000	10000	10100
30204	100030	40101	10101	20000	10000	100	20000	10017	300	1546384	2578617	30146	200	10021	20039	200	10002	20002	10001	10000	10000	10100
30204	100030	40101	10101	20000	10000	100	20000	10000	300	1546174	2578264	30100	200	10002	20002	200	10002	20002	10001	10000	10000	10100
30204	100030	40101	10101	20000	10000	100	20000	10018	307	1547441	2580309	30148	202	10022	20040	200	10002	20002	10001	10000	10000	10100
30205	100072	40108	10103	20003	10002	100	20029	10000	300	1546174	2578264	30100	200	10002	20002	200	10002	20004	10001	10000	10000	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 10.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
30024	100031	40011	10011	20000	10000	10	20000	10001	30	1546176	2578264	30011	20	10002	20004	20	10000	20000	10001	10000	10000	10010
30024	100030	40011	10011	20000	10000	10	20000	10000	30	1546174	2578264	30010	20	10000	20000	20	10000	20000	10001	10000	10000	10010
30024	100030	40011	10011	20000	10000	10	20000	10000	30	1546174	2578264	30010	20	10000	20000	20	10000	20000	10001	10000	10000	10010
30024	100030	40011	10011	20000	10000	10	20000	10000	30	1546174	2578264	30010	20	10000	20000	20	10000	20000	10001	10000	10000	10010
30024	100048	40011	10011	20000	10000	10	20000	10000	30	1546174	2578264	30010	20	10000	20000	20	10000	20000	10001	10000	10000	10010
30024	100030	40011	10011	20000	10000	10	20000	10000	30	1546174	2578264	30010	20	10000	20000	20	10000	20000	10001	10000	10000	10010
30024	100030	40011	10011	20000	10000	10	20000	10000	30	1546174	2578264	30010	20	10000	20000	20	10000	20000	10001	10000	10000	10010
30024	100030	40011	10011	20000	10000	10	20000	10019	30	1546396	2578617	30058	20	10022	20042	20	10000	20000	10001	10000	10000	10010
30024	100030	40011	10011	20000	10000	10	20000	10000	30	1546174	2578264	30010	20	10000	20000	20	10000	20000	10001	10000	10000	10010
30024	100030	40011	10011	20000	10000	10	20000	10000	30	1546174	2578264	30010	20	10000	20000	20	10000	20000	10001	10000	10000	10010

Test 3: throughput

Count: 8

Code:

  ucvtf d0, w8, #3
  ucvtf d1, w8, #3
  ucvtf d2, w8, #3
  ucvtf d3, w8, #3
  ucvtf d4, w8, #3
  ucvtf d5, w8, #3
  ucvtf d6, w8, #3
  ucvtf d7, w8, #3

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160204	40148	160117	101	80007	80009	100	80013	80012	300	240036	640080	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40103	160115	101	80006	80008	100	80012	80012	300	240036	640080	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40090	160115	101	80006	80008	100	80012	80012	300	240036	640080	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40090	160115	101	80006	80008	100	80012	80012	300	240036	640080	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40090	160115	101	80006	80008	100	80012	80012	300	240036	640080	160124	200	80012	80012	200	80054	80054	1	80000	80000	100
160204	40090	160115	101	80006	80008	100	80012	80012	300	240036	640080	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40090	160115	101	80006	80008	100	80012	80012	300	240036	640080	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40090	160115	101	80006	80008	100	80012	80012	300	240914	641748	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40090	160115	101	80006	80008	100	80012	80012	300	240036	640080	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40090	160115	101	80006	80008	100	80012	80012	300	240036	640080	160124	200	80012	80012	200	80012	80012	1	80000	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160024	40469	160027	11	80007	80009	10	80013	80012	30	240036	640080	160034	20	80012	80012	20	80012	80012	1	80000	80000	10
160024	40072	160011	11	80000	80000	10	80000	80000	30	240000	640000	160010	20	80000	80000	20	80054	80054	1	80000	80000	10
160024	40048	160011	11	80000	80000	10	80000	80000	30	240000	640000	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40042	160011	11	80000	80000	10	80000	80000	30	240000	640000	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40042	160011	11	80000	80000	10	80000	80000	30	250619	658619	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40042	160011	11	80000	80000	10	80000	80000	30	240000	640000	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40042	160011	11	80000	80000	10	80000	80000	30	240630	640614	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40151	160011	11	80000	80000	10	80000	80013	30	240039	640088	160036	20	80013	80013	20	80000	80000	1	80000	80000	10
160024	40048	160011	11	80000	80000	10	80000	80000	30	240000	640000	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40046	160011	11	80000	80000	10	80000	80000	30	240000	640000	160010	20	80000	80000	20	80000	80000	1	80000	80000	10

UCVTF (scalar, fixed-point, D from W)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations