Icestorm: UCVTF (scalar, fixed-point, S from W) measurements

Code:

  ucvtf s0, w0, #3

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)
2004	633	2001	1	1000	1000	1000	1000	3000	8000	2000	1000	1000	1000	1000	1	1000	1000
2004	538	2001	1	1000	1000	1000	1000	3000	8000	2000	1000	1000	1000	1000	1	1000	1000
2004	538	2001	1	1000	1000	1000	1000	3000	8000	2000	1000	1000	1000	1000	1	1000	1000
2004	537	2001	1	1000	1000	1000	1000	3000	8000	2000	1000	1000	1000	1000	1	1000	1000
2004	539	2001	1	1000	1000	1000	1000	3000	8000	2000	1000	1000	1000	1000	1	1000	1000
2004	537	2001	1	1000	1000	1000	1000	3000	8000	2000	1000	1000	1000	1000	1	1000	1000
2004	537	2001	1	1000	1000	1000	1000	3000	8000	2000	1000	1000	1000	1000	1	1000	1000
2004	537	2001	1	1000	1000	1000	1000	3000	8000	2000	1000	1000	1000	1000	1	1000	1000
2004	537	2001	1	1000	1000	1000	1000	3000	8000	2000	1000	1000	1000	1000	1	1000	1000
2004	537	2001	1	1000	1000	1000	1000	3000	8000	2000	1000	1000	1000	1000	1	1000	1000

Test 2: Latency 1->2 roundtrip

Code:

  ucvtf s0, w0, #3
  fmov x0, d0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 10.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
30204	100030	40101	10101	20000	10000	100	20000	10001	300	1546172	2578264	30101	200	10002	20004	200	10002	20004	10001	10000	10000	10100
30204	100030	40101	10101	20000	10000	100	20000	10000	300	1546174	2578264	30100	200	10002	20002	200	10002	20002	10001	10000	10000	10100
30204	100030	40101	10101	20000	10000	100	20000	10000	300	1546174	2578264	30100	200	10002	20002	200	10002	20002	10001	10000	10000	10100
30205	100063	40108	10103	20003	10002	100	20029	10000	300	1546174	2578264	30100	200	10002	20002	200	10002	20002	10001	10000	10000	10100
30204	100030	40101	10101	20000	10000	100	20000	10000	300	1546174	2578264	30100	200	10002	20002	200	10002	20002	10001	10000	10000	10100
30204	100030	40101	10101	20000	10000	100	20000	10000	300	1546174	2578264	30100	200	10002	20002	200	10002	20002	10001	10000	10000	10100
30204	100030	40101	10101	20000	10000	100	20000	10000	300	1546174	2578264	30100	200	10002	20002	200	10002	20002	10001	10000	10000	10100
30204	100030	40101	10101	20000	10000	100	20000	10000	300	1546174	2578264	30100	200	10002	20002	200	10002	20002	10001	10000	10000	10100
30204	100033	40101	10101	20000	10000	100	20000	10000	300	1546270	2578420	30100	200	10002	20002	200	10021	20039	10003	10000	10000	10100
30204	100030	40101	10101	20000	10000	100	20000	10000	300	1546174	2578264	30100	200	10002	20002	200	10002	20002	10001	10000	10000	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 10.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
30024	100036	40011	10011	20000	10000	10	20000	10000	30	1546168	2578264	30010	20	10000	20000	20	10000	20000	10001	10000	10000	10010
30024	100030	40011	10011	20000	10000	10	20000	10000	30	1546174	2578264	30010	20	10000	20000	20	10000	20000	10001	10000	10000	10010
30024	100030	40011	10011	20000	10000	10	20000	10017	30	1546467	2578747	30056	20	10021	20039	20	10000	20000	10001	10000	10000	10010
30024	100030	40011	10011	20000	10000	10	20000	10000	30	1546174	2578264	30010	20	10000	20000	20	10000	20000	10001	10000	10000	10010
30024	100030	40011	10011	20000	10000	10	20000	10000	30	1546174	2578264	30010	20	10000	20000	20	10000	20000	10001	10000	10000	10010
30024	100030	40011	10011	20000	10000	10	20000	10000	30	1546174	2578264	30010	20	10000	20000	20	10000	20000	10001	10000	10000	10010
30024	100030	40011	10011	20000	10000	10	20000	10000	30	1546174	2578264	30010	20	10000	20000	20	10000	20000	10001	10000	10000	10010
30025	100063	40018	10013	20003	10002	10	20029	10000	30	1546500	2578784	30010	20	10000	20000	20	10000	20000	10001	10000	10000	10010
30025	100072	40018	10013	20003	10002	10	20029	10000	30	1546174	2578264	30010	20	10000	20000	20	10000	20000	10001	10000	10000	10010
30024	100030	40011	10011	20000	10000	10	20000	10000	30	1546174	2578264	30010	20	10000	20000	20	10000	20000	10001	10000	10000	10010

Test 3: throughput

Count: 8

Code:

  ucvtf s0, w8, #3
  ucvtf s1, w8, #3
  ucvtf s2, w8, #3
  ucvtf s3, w8, #3
  ucvtf s4, w8, #3
  ucvtf s5, w8, #3
  ucvtf s6, w8, #3
  ucvtf s7, w8, #3

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5012

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160204	40235	160115	101	80006	80008	100	80012	80012	300	240036	640080	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40090	160115	101	80006	80008	100	80012	80012	300	245205	648245	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160205	40164	160175	101	80036	80038	100	80054	80181	307	247593	650310	160464	202	80181	80181	200	80012	80012	1	80000	80000	100
161452	45549	161395	816	80037	80542	810	80055	80012	300	240036	640080	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40097	160115	101	80006	80008	100	80012	80012	300	244958	646484	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40112	160115	101	80006	80008	100	80012	80012	300	240818	641661	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40205	160175	101	80036	80038	100	80054	80012	300	240036	640080	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40090	160115	101	80006	80008	100	80012	80012	300	240036	640080	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40093	160115	101	80006	80008	100	80012	80096	300	250572	655107	160292	200	80096	80096	200	80264	80264	1	80000	80000	100
160204	40499	160295	101	80096	80098	100	80138	80096	300	244291	645309	160292	200	80096	80096	200	80012	80012	1	80000	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160024	40572	160027	11	80007	80009	10	80013	80012	30	240258	640286	160034	20	80012	80012	20	80000	80000	1	80000	80000	10
160024	40061	160011	11	80000	80000	10	80000	80000	30	240000	640000	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40046	160011	11	80000	80000	10	80000	80000	30	240000	640000	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40046	160011	11	80000	80000	10	80000	80000	30	240000	640000	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160025	40105	160085	11	80036	80038	10	80054	80000	30	243824	643788	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40052	160011	11	80000	80000	10	80000	80000	30	240000	640000	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40046	160011	11	80000	80000	10	80000	80000	30	242591	642591	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40049	160011	11	80000	80000	10	80000	80000	30	240000	640000	160010	20	80000	80000	20	80054	80054	1	80000	80000	10
160024	40048	160011	11	80000	80000	10	80000	80000	30	240000	640000	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40049	160011	11	80000	80000	10	80000	80000	30	244554	652513	160010	20	80000	80000	20	80000	80000	1	80000	80000	10

UCVTF (scalar, fixed-point, S from W)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations