Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

UCVTF (scalar, integer, S from W)

Test 1: uops

Code:

  ucvtf s0, w0
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch simd uop (57)dispatch ldst uop (58)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
20045742001110001000100010003000800020001000100010001000110001000
20045402001110001000100010003000800020001000100010001000110001000
20045372001110001000100010003496849620001000100010001000110001000
20045372001110001000100010004672967220001000100010001000110001000
20045372001110001000100010003000800020001000100010001000110001000
20045372001110001000100010003000800020001000100010001000110001000
20045372001110001000100010003000800020001000100010001000110001000
20045372001110001000100010003000800020001000100010001000110001000
20045372001110001000100010003000800020001000100010001000110001000
20045372001110001000100010003000800020001000100010001000110001000

Test 2: Latency 1->2 roundtrip

Code:

  ucvtf s0, w0
  fmov x0, d0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 10.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
3020410003040101101012000010000100200001001830015463822578617301472001002120041200100022000210001100001000010100
3020410003040101101012000010000100200001000030015461742578264301002001000220002200100202003710002100001000010100
3020410003040101101012000010000100200001000030015461742578264301002001000220002200100022000210001100001000010100
3020510010940108101032000310002100200291000030015462252578342301002001000220002200100022000210001100001000010100
3020510006340108101032000310002100200291000130015461762578264301012001000220004200100202003910002100001000010100
3020410003240101101012000010000100200001000030015461742578264301002001000220002200100212003910002100001000010100
3020410004540101101012000010000100200001000030015461742578264301002001000220002200100022000210001100001000010100
3020410003040101101012000010000100200001000030015462542578394301002001000220002200100212003910003100001000010100
3020410004640101101012000010000100200001000030015461742578264301002001000220002200100022000210001100001000010100
3020410003040101101012000010000100200001000130015461722578264301012001000220004202100202003810004100001000010100

1000 unrolls and 10 iterations

Result (median cycles for code): 10.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
300251000764001810013200031000210200291000130154624025783683001120100022000420100002000010001100001000010010
300241000304001110011200001000010200001000030154617425782643001020100002000020100002000010001100001000010010
300241000304001110011200001000010200001000030154617425782643001020100002000020100002000010001100001000010010
300241000304001110011200001000010200001000030154617425782643001020100002000020100002000010001100001000010010
300241000304001110011200001000010200001000030154617425782643001020100002000020100002000010001100001000010010
300241000304001110011200001000010200001000030154617425782643001020100002000020100222004210003100001000010010
300241000304001110011200001000010200001000030154617425782643001020100002000020100002000010001100001000010010
300241000304001110011200001000010200001000030154617425782643001020100002000020100002000010001100001000010010
300241000304001110011200001000010200001000030154617425782643001020100002000020100002000010001100001000010010
300241000304001110011200001000010200001000030154617425782643001020100002000020100002000010001100001000010010

Test 3: throughput

Count: 8

Code:

  ucvtf s0, w8
  ucvtf s1, w8
  ucvtf s2, w8
  ucvtf s3, w8
  ucvtf s4, w8
  ucvtf s5, w8
  ucvtf s6, w8
  ucvtf s7, w8
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
16020440157160115101800068000810080012800123002400366400801601242008001280012200800128001218000080000100
16020440097160115101800068000810080012800123002400366400801601242008001280012200800128001218000080000100
16020440090160115101800068000810080012800123002400366400801601242008001280012200800128001218000080000100
16020440090160115101800068000810080012800543002402706404641602082008005480054200800128001218000080000100
16020440090160115101800068000810080012800123002400366400801601242008001280012200800128001218000080000100
16020440090160115101800068000810080012800123002400366400801601242008001280012200800128001218000080000100
16020440090160115101800068000810080012800123002426266442591601242008001280012200800128001218000080000100
16020440095160115101800068000810080012800123002400366400801601242008001280012200800128001218000080000100
16020440090160115101800068000810080012800123002400366400801601242008001280012200800128001218000080000100
16020440090160115101800068000810080012800123002400366400801601242008001280012200800128001218000080000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
16002440425160027118000780009108001380000302400006400001600102080000800002080000800001800008000010
16002440061160011118000080000108000080000302400006400001600102080000800002080000800001800008000010
16002440046160011118000080000108000080000302400006400001600102080000800002080000800001800008000010
16002440046160011118000080000108000080000302400006400001600102080000800002080000800001800008000010
16002440046160011118000080000108000080000302400006400001600102080000800002080000800001800008000010
16002440079160011118000080000108000080000302400006400001600102080000800002080000800001800008000010
16002440066160011118000080000108000080000302862637068321600102080000800002080000800001800008000010
16002440067160011118000080000108000080000302472376552271600102080000800002080000800001800008000010
16002440046160011118000080000108000080000302400006400001600102080000800002080000800001800008000010
16002440046160011118000080000108000080000302400006400001600102080000800002080000800001800008000010