Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

UCVTF (vector, integer, 2D from 2D)

Test 1: uops

Code:

  ucvtf v0.2d, v0.2d
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)dispatch uop (78)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
10043033100111000100075905100010000010001010000
10043033100111000100075905100010000010001010000
10043033100111000100075905100010000010001010000
10043033100111000100075905100010000010001010000
10043033100111000100075905100010000010001010000
10043033100111000100075905100010000010001010000
10043033100111000100075905100010000010001010000
10043033100111000100075905100010000010001010000
10043033100111000100075905100010000010001010000
10043033100111000100075905100010000010001010000

Test 2: Latency 1->2

Code:

  ucvtf v0.2d, v0.2d
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020430033101011011000010010000300768905101002001000620010006110000100
1020430033101011011000010010000300768905101002001000420010004110000100
1020430033101011011000010010000300768905101002001000420010004110000100
1020430033101011011000010010000300768905101002001000420010004110000100
1020430033101011011000010010000300768905101002001000420010004110000100
1020430033101011011000010010000300768905101002001000420010004110000100
1020430033101011011000010010000300768905101002001000420210046210000100
1020430033101011011000010010000300768905101002001000420010004110000100
1020430033101011011000010010000300768905101002001000420010004110000100
1020430033101011011000010010000300768905101002001000420010004110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
1002430033100212110000201000070768905100202010006200100001101000010
1002430033100212110000201000070768905100202010000200100001101000010
1002430033100212110000201000070768905100202010000200100001101000010
1002430033100212110000201000070768905100202010000200100001101000010
1002430033100212110000201000070768905100202010000200100001101000010
1002430033100212110000201000070768905100202010000200100001101000010
1002430033100212110000201000070768905100202010000200100441101000010
1002430033100212110000201000070768905100202010000200100001101000010
1002430033100212110000201000070768905100202010000200100001101000010
1002430033100212110000201000070768905100202010000200100001101000010

Test 3: throughput

Count: 8

Code:

  ucvtf v0.2d, v8.2d
  ucvtf v1.2d, v8.2d
  ucvtf v2.2d, v8.2d
  ucvtf v3.2d, v8.2d
  ucvtf v4.2d, v8.2d
  ucvtf v5.2d, v8.2d
  ucvtf v6.2d, v8.2d
  ucvtf v7.2d, v8.2d
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
802044008380107101800061008001030032003680108200800122000800121080000100
802044004580105101800041008000830032003680108200800122000800121080000100
802044003580105101800041008000830032003680108200800122000800121080000100
802044003580105101800041008000830032003680108200800122000800121080000100
802044003580105101800041008000830032003680108200800122000800641080000100
802044003580105101800041008000830032003680108200800122000800121080000100
802044003580107101800061008001030032003680108200800122000800121080000100
802044003580105101800041008000830032003680108200800122000800121080000100
802044003580105101800041008000830032003680108200800122000800121080000100
802044003580105101800041008000830032003680108200800122000800121080000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
80024401818002721800062080010703200528003220800182080000118000010
80024400368002121800002080000703200008002020800002080000118000010
80024400358002121800002080000703200008002020800002080000118000010
80024400358002121800002080000703200008002020800002080000118000010
80024400358002121800002080000703200008002020800002080000118000010
80024400358002121800002080000703200008002020800002080000118000010
80024400358002121800002080000703200008002020800002080000118000010
80024400358002121800002080000703200008002020800002080000118000010
80024400358002121800002080000703200008002020800002080000118000010
80024400358002121800002080000703202168007620800682080000118000010