Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

UMAXV (vector, 8B)

Test 1: uops

Code:

  umaxv b0, v0.8b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000

Test 2: Latency 1->2

Code:

  umaxv b0, v0.8b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	30033	10101	101	10000	0	100	10000	300	768905	10100	200	10006	200	20008	1	10000	100
10204	30033	10101	101	10000	0	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	0	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	0	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	0	100	10000	300	768905	10100	200	10004	202	20092	2	10000	100
10204	30033	10101	101	10000	0	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	0	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	0	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	0	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	0	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10025	30066	10027	21	10006	20	10031	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10

Test 3: throughput

Count: 8

Code:

  umaxv b0, v8.8b
  umaxv b1, v8.8b
  umaxv b2, v8.8b
  umaxv b3, v8.8b
  umaxv b4, v8.8b
  umaxv b5, v8.8b
  umaxv b6, v8.8b
  umaxv b7, v8.8b

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80204	40095	80107	101	80006	100	80010	0	300	0	320036	80108	200	0	80012	200	0	160028	1	0	80000	100
80204	40035	80107	101	80006	100	80010	0	300	0	320036	80108	200	0	80012	200	0	160024	1	0	80000	100
80204	40035	80105	101	80004	100	80008	0	300	0	320036	80108	200	0	80012	200	0	160024	1	0	80000	100
80204	40035	80105	101	80004	100	80008	0	300	0	320036	80108	200	0	80012	200	0	160024	1	0	80000	100
80204	40035	80105	101	80004	100	80008	0	300	0	320036	80108	200	0	80012	200	0	160024	1	0	80000	100
80204	40035	80105	101	80004	100	80008	0	300	0	320044	80110	200	0	80014	200	0	160024	1	0	80000	100
80204	40035	80105	101	80004	100	80008	0	300	0	320036	80108	200	0	80012	200	0	160024	1	0	80000	100
80204	40035	80105	101	80004	100	80008	0	300	0	320036	80108	200	0	80012	200	0	160024	1	0	80000	100
80204	40035	80105	101	80004	100	80008	0	300	0	320044	80110	200	0	80014	200	0	160028	1	0	80000	100
80204	40045	80105	101	80004	100	80008	0	300	0	320036	80108	200	0	80012	200	0	160024	1	0	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
80024	40123	80029	21	80008	20	80012	70	320000	80020	20	80000	20	160000	11	80000	10
80024	40035	80021	21	80000	20	80000	70	320000	80020	20	80000	20	160000	11	80000	10
80024	40035	80021	21	80000	20	80000	70	320000	80020	20	80000	20	160000	11	80000	10
80024	40035	80021	21	80000	20	80000	70	320000	80020	20	80000	20	160000	11	80000	10
80024	40035	80021	21	80000	20	80000	70	320000	80020	20	80000	20	160000	11	80000	10
80024	40035	80021	21	80000	20	80000	70	320000	80020	20	80000	20	160000	11	80000	10
80024	40035	80021	21	80000	20	80000	70	320208	80074	20	80066	20	160000	11	80000	10
80024	40035	80021	21	80000	20	80000	70	320000	80020	20	80000	20	160000	11	80000	10
80024	40035	80021	21	80000	20	80000	70	320000	80020	20	80000	20	160000	11	80000	10
80024	40035	80021	21	80000	20	80000	70	320000	80020	20	80000	20	160000	11	80000	10